• Proceedings of the Korea Contents Association Conference
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• 2005.05a
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• pp.362-368
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• 2005

This paper is related to the fast block matching algorithm, especially a method for expanding the search pattern using the second local matching point in the adaptive hexagonal search. To reduce the local minima problem in fast motion estimation, the proposed method expands the search pattern by adding new searching points selected by using the second local matching point to conventional search pattern formed by the first local matching point in the adaptive hexagonal search. According to estimating the motion vector by applying block matching algorithm based on hexagonal search to the expanded search pattern, the proposed method can effectively carry out fast motion estimation to improve the performance in terms of compensated image quality.

• KIISE Transactions on Computing Practices
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• v.21 no.2
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• pp.126-131
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• 2015

As flash-based storage systems have been actively employed in large-scale servers and data centers, reliability has become an indispensable element. One promising technique for enhancing reliability is static wear-leveling, which distributes erase operations evenly among blocks so that the lifespan of storage systems can be prolonged. However, increasing the capacity makes the processing overhead of this technique non-trivial, mainly due to searching for blocks whose erase count would be minimum (or maximum) among all blocks. To reduce this overhead, we introduce a new randomized block selection method in static wear-leveling. Specifically, without exhaustive search, it chooses n blocks randomly and selects the maximal/minimal erased blocks among the chosen set. Our experimental results revealed that, when n is 2, the wear-leveling effects can be obtained, while for n beyond 4, the effect is close to that obtained from traditional static wear-leveling. For quantitative evaluation of the processing overhead, the scheme was actually implemented on an FPGA board, and overhead reduction of more than 3 times was observed. This implies that the proposed scheme performs as effectively as the traditional static wear-leveling while reducing overhead.

• Journal of Broadcast Engineering
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• v.16 no.4
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• pp.669-679
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• 2011

In this paper, we propose a POCS based irregularly sampled image interpolation method exploiting non-local block-based wavelet shrinkage denoising algorithm. The method provides convex sets to improve the performance. The Delaunay triangulation interpolation is first applied to interpolate the missing pixels of the irregularly sampled image into the regular grids. Then, the non-local block-based wavelet shrinkage denoising algorithm is applied, and the originally observed pixels are enforced. After iteration is performed, the denoising algorithm for non-edge areas is applied to acquire the final result. The experimental results show that the proposed method outperforms the conventional methods.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2021.06a
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• pp.26-27
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• 2021

본 논문에서는 자막방송 제공을 위해 방송콘텐츠를 이해하는 방법으로 잔차 합성곱 순환신경망 기반 음향 사건 분류 기법을 제안한다. 제안된 기법은 잔차 합성곱 신경망과 순환 신경망을 연결한 구조를 갖는다. 신경망의 입력 특징으로는 멜-필터벵크 특징을 활용하고, 잔차 합성곱 신경망은 하나의 스템 블록과 5개의 잔차 합성곱 신경망으로 구성된다. 잔차 합성곱 신경망은 잔차 학습으로 구성된 합성곱 신경망과 기존의 합성곱 신경망 대비 특징맵의 표현 능력 향상을 위해 합성곱 블록 주의 모듈로 구성한다. 추출된 특징맵은 순환 신경망에 연결되고, 최종적으로 음향 사건 종류와 시간정보를 추출하는 완전연결층으로 연결되는 구조를 활용한다. 제안된 모델 훈련을 위해 라벨링되지 않는 데이터 활용이 가능한 평균 교사 모델을 기반으로 훈련하였다. 제안된 모델의 성능평가를 위해 DCASE 2020 챌린지 Task 4 데이터 셋을 활용하였으며, 성능 평가 결과 46.8%의 이벤트 단위의 F1-score를 얻을 수 있었다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.1
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• pp.49-58
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• 2000

This paper presents a new color Image coding method which estimates color component Images from luminance image using spectral correlation m wavelet transformed domain More specifically, the wavelet transform is performed to the luminance image(Y), and then, for an efficient quad-tree division to encompass the varying block size, a cost function IS defined using high frequency coefficients generated by wavelet decomposition Next, a scale factor and an offset factor for each the block to minimize the estimation error between luminance image(Y) and R, B Images, are iteratively calculated With respect to the varying block size With associated cost function.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.67-74
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• 2008

A compact and high-performance AES(Advanced Encryption Standard) encryption/decryption processor is designed by applying various hardware sharing and optimization techniques. In order to achieve minimized hardware complexity, sharing the S-Boxes for round transformation with the key scheduler, as well as merging and reusing datapaths for encryption and decryption are utilized, thus the area of S-Boxes is reduced by 25%. Also, the S-Boxes which require the largest hardware in AES processor is designed by applying composite field arithmetic on $GF(((2^2)^2)^2)$, thus it further reduces the area of S-Boxes when compared to the design based on $GF(2^8)$ or $GF((2^4)^2)$. By optimizing the operation of the 64-bit round transformation and round key scheduling, the round transformation is processed in 3 clock cycles and an encryption of 128-bit data block is performed in 31 clock cycles. The designed AES processor has about 15,870 gates, and the estimated throughput is 412.9 Mbps at 100 MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.5
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• pp.477-485
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• 2002

In this paper, we present an efficient hardware architecture for the H.263 video codec and its VLSI implementation. This architecture is based on the unified interface by which internal hardware engines and an internal RISC processor are connected one another. The unified interface enables the modular design of internal blocks, efficient hardware/software partitioning, and pipelined paralled operations. The developed VLSI supports the H.263 version 2 profile 3 @ level 10, and moreover, both the control protocol H.245 and the multiplexing protocol H.223. Therefore, it can be used for the complete ITU-T H.324 or 3GPP 3G 324M multimedia processor with the help of an external audio codec. Simultaneous encoding and decoding of QCIF format images at a rate greater than 15 frames per second is achieved at 40 MHz clock frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.36-42
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• 2016

In multi-level-cell based storage devices, TLC NAND has been employed solid state drive due to cost effectiveness. Since TLC has slow performance and low endurance compared with MLC, TLC based storage has adopted SLC buffer scheme to improve performance. To improve SLC buffer scheme, this paper proposes page overwriting method in SLC block. This method provides data updates without erase operation within a limited number. When SLC buffer area is filled up, FTL should execute copying valid pages and erasing it. The proposed method reduces erase counts by 50% or more compared with previous SLC buffer scheme. Simulation results show that the proposed SLC buffer overwrite method achieves 2 times write performance improvement.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.4
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• pp.50-57
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• 2009

This paper presents a new model-based macroblock layer rate control algorithm for low bit rate video coding which generates output bits corresponding to a target bit budget. The H.264 standard uses various coding modes and optimization methods to improve the compression performance, which makes it difficult to control the generated traffic accurately in low bit rate environments. In the proposed scheme, we first estimate MAD values of macroblocks in a frame and define a target remaining bits using the estimated MAD values before encoding each macroblock. If a difference between the target value and the actual value is greater than a threshold value, the quantization parameter is adjusted to decrease the difference. It is shown by experimental results that the new algorithm can obtain more than 66% decrease of the difference between the target bits and the resulting bits for a frame with the PSNR performance better than that of the existing rate control algorithm.

• Journal of Convergence for Information Technology
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• v.11 no.6
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• pp.270-281
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• 2021

With the development of information technology, the size of insurance fraud is increasing rapidly every year, and the method is being organized and advanced in conspiracy. Although various forms of prediction models are being studied to predict and detect this, insurance-related information is highly sensitive, which poses a high risk of sharing and access and has many legal or technical constraints. In this paper, we propose a machine learning insurance fraud prediction model based on blockchain, one of the most popular technologies with the recent advent of the Fourth Industrial Revolution. We utilize blockchain technology to realize a safe and trusted insurance information sharing system, apply the theory of social relationship analysis for more efficient and accurate fraud prediction, and propose machine learning fraud prediction patterns in four stages. Claims with high probability of fraud have the effect of being detected at a higher prediction rate at an earlier stage, and claims with low probability are applied differentially for post-reference management. The core mechanism of the proposed model has been verified by constructing an Ethereum local network, requiring more sophisticated performance evaluations in the future.