• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.4159-4164
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• 2012

This paper presents a chaotic circuit with voltage controllability for secure communication applications. The proposed circuit which has two control voltages consists of the nonlinear function block(NFB) with three MOS transistors, one source follower and non-overlapping two-phase clock generator for sample and hold. By SPICE simulation, chaotic dynamics such as time waveform, frequency analysis and bifurcations were analyzed. SPICE results showed that proposed circuit can make various chaotic signals by control voltage.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2006.11a
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• pp.73-76
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• 2006

H.264는 MPEG-2, MPEG-4 Part 2, H.263 등 기존의 비디오 압축 표준들에 비해 우수한 화질과 부호화 효율을 제공하여 차세대 비디오 압축 표준으로서 널리 사용될 전망이다. 현재 H.264표준화 그룹인 JVT에서는 디지털 시네마 영상을 위한 Advanced 4:4:4 프로파일에 대한 표준화가 진행 중이다. 이 프로파일은 기존의 프로파일과 달리 화소당 8-12비트의 영상을 지원하며, YUV 영상대신 RGB 영상을 입력영상으로 사용한다. 디지털 시네마 영상은 보통 HD급 이상의 화면 크기를 가지며 초당 24Hz의 프레임율을 가진다. 이러한 영상에서는 화소간의 공간적 유사성이 매우 높아지는 경향이 있으며, 30Hz 영상에 비해 시간적 유사성이 감소하는 경향이 있다. 그 결과 H.264로 디지털 시네마 영상 압축 시, 공간 예측을 통한 Intra 매크로블록의 비율이 다른 테스트 영상들에 비해 월등히 높다는 것을 알 수 있다. 이는 디지털 시네마 영상 압축 시, 화면간 예측을 수행하는 ME/MC에 비해 공간 예측이 효율적이다는 것을 입증한다. 화면간 예측의 성능을 향상하기 위해 본 논문에서는 ME/MC 후 생성된 잔차 신호들을 간단히 변환하는 방법을 제안한다. 간단한 변환 기술이 추가되어 화면간 예측의 압축 성능이 향상됨은 물론, Inter 프레임에서 화면간 예측과 공간예측을 모두 사용하였을 때 전체적인 압축성능이 향상함을 실험을 통하여 확인 할 수 있었다.

• Aerospace Engineering and Technology
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• v.11 no.2
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• pp.73-79
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• 2012

Because the contact time between satellite and ground station is very limited in LEO (Low Earth Orbit) satellite, all telemetry data generated on spacecraft bus are stored in a mass memory and downlinked to the ground together with real time data during the contact time. The mass memory is initialized in the first system initialization phase and the page status of each memory block is generated step by step. After the completion of the system initialization, the telemetry data are continuously stored and the stored data are played back to the ground by command. And the memory scrubbing is periodically performed for correction of single bit error which can be generated on harsh space environment. This paper introduces the mass memory operation method for telemetry processing of LEO satellite. It includes a general mass memory data structure, the methods of mass memory initialization, scrubbing, data storage and downlink, and mass memory management of primary and redundant mass memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6A
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• pp.555-561
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• 2002

In this paper, a new designed circuit of highly parallel multiplier using standard basis over $GF(2^m)$ is presented. Prior to construct the multiplier circuit, we provide the Vector Code Generate Module(VCGM) that generate each vector codes for multiplication. Using these VCGMs, we can get all vector codes necessary for operation and modular sum up each independent corresponding basis, respectively. Following the equations in this paper, we can design generalized multiplier to m. For the proposed circuit in this parer, we show the example in $GF(2^4)$ using VCGMs. In this paper, we build a multiplier with VCGMs, AND blocks, and EX-OR blocks. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer then other circuit. We verify the proposed circuit by functional simulation and show its result. Finally, we compare the circuit composition with other works and show its result with a table.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2367-2372
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• 2015

One of various low-density parity-check(LDPC) codes that has been adopted in many communication standards due to its error correction ability is a quasi-cyclic LDPC(QC-LDPC) code, which leads to comparable decoder complexity. One of the main blocks in the QC-LCDC code decoder is a multi-size circular shifter(MSCS) that can perform various size rotation. The MSCS can be implemented with many structures, one of which is based on Banes network. The Benes network structure can perform the normal MSCS operation efficiently, but it cannot use the properties coming from specifications like rotation sizes. This paper proposesd a scheme where the Benes network structure can use the rotation size property with the modification of the control signal generation. The proposed scheme is applied to the MSCS of IEEE 802.16e WiMAX QC-LDPC decoder to reduce the number of MUXes and the critical path delay.

• The KIPS Transactions:PartC
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• v.13C no.7 s.110
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• pp.843-850
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• 2006

This is devoted to first, to propose a hash chain algorithm that generates more secure key than conventional encryption method. Secondly, we proposes encryption method that is more secure than conventional system using a encryption method that encrypts each block with each key generated by a hash chain algorithm. Thirdly, After identifying the user via wired and wireless network using a user authentication method. We propose a divided session key method so that Although a client key is disclosed, Attackers cannot catch a complete key and method to safely transfer the key using a divided key method. We make an experiment using various size of digital contents files for performance analysis after performing the design and implementation of system. Proposed system can distribute key securely than conventional system and encrypt data to prevent attacker from decrypting complete data although key may be disclosed. The encryption and decryption time that client system takes to replay video data fie is analogous to the conventional method.

• Journal of Korea Multimedia Society
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• v.14 no.5
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• pp.614-621
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• 2011

This paper presents design of a wide tuning range digitally controlled oscillator(DCO) for Mobile-DTV applications. DCO is the key element of the ADPLL block that generates oscillation frequencies. We proposed a binary delay chain(BDC) structure, for wide tuning range DCO, modifying conventional fixed delay chain. The proposed structure generates oscillation frequencies by delay cell combination which has a variable delay time of $2^i$ in the range of $0{\leq}i{\leq}n-1$. The BOC structure can reduce the number of delay cells because it make possible to select delay cell and resolution. We simulated the proposed DCO by Cadence's Spectre RF tool in 1.8V chartered $0.18{\mu}m$ CMOS process. The simulation results showed 77MHz~2.07GHz frequency range and 3ps resolution. The phase noise yields -101dBc/Hz@1MHz at Mobile-DTV maximum frequency 1675MHz and the power consumption is 5.87mW. The proposed DCO satisfies Mobile-DTV standards such as ATSC-M/H, DVB-H, ISDB-T, T-DMB.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.1
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• pp.64-72
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• 2001

This paper is on a design of the high-speed cipher IC using IDEA algorithm. The chip is consists of six functional blocks. The principal blocks are encryption and decryption key generator, input data circuit, encryption processor, output data circuit, operation mode controller. In subkey generator, the design goal is rather decrease of its area than increase of its computation speed. On the other hand, the design of encryption processor is focused on rather increase of its computation speed than decrease of its area. Therefore, the pipeline architecture for repeated processing and the modular multiplier for improving computation speed are adopted. Specially, there are used the carry select adder and modified Booth algorithm to increase its computation speed at modular multiplier. To input the data by 8-bit, 16-bit, 32-bit according to the operation mode, it is designed so that buffer shifts by 8-bit, 16-bit, 32-bit. As a result of simulation by 0.25 $\mu\textrm{m}$ process, this IC has achieved the throughput of 1Gbps in addition to its small area, and used 12,000gates in implementing the algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.34-44
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• 2006

A system-on-a-chip (SoC) design uses pre-verified IP hardware blocks in order to reduce design time. We need interface circuits to connect IPs with different protocols. In SoC design we should design interface circuits frequently and these tasks are somewhat time-consuming and error-prone. So it is necessary to generate the interface circuits automatically. Several studies have been made on generating interface circuits only from the communication protocols of IPs. With existing approaches, it is not easy to generate interface circuits connecting two IPs only from communication protocols: connection between IP with address and W without address, connection between IP with only one port to transfer address/data and IP with different ports for address and data connection between IP that transfer address and data together and IP that transfer only one address with a number of data in a burst. No consideration of various characteristics of IPs and no changed algorithm are responsible for it. In order to solve this problem, the proposed approach categorizes communication protocols of IPs, and takes characteristics matching of IPs into account during the interface synthesis. In experiments, we show that we could correctly generate and verify interface circuits for IPs with different characteristics.

• Journal of the Korea Society for Simulation
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• v.22 no.4
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• pp.109-118
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• 2013

This paper adopts the system configuration to assess the reliability instead of making a fault tree (FT), which is a traditional method to analyze reliability of a certain system; this is the reliability block diagram (RBD) method. The RBD method is a graphical presentation of a system diagram connecting the subsystems of components according to their functions or reliability relationships. The equipment model for the reliability simulation is modeled based on the discrete event system specification (DEVS) formalism. In order to make various alternatives of target system, this paper also adopts the system entity structure (SES), an ontological framework that hierarchically represents the elements of a system and their relationships. To enhance the calculation time of reliability analysis, GPU-based accelerations are adopted to the reliability simulation.