• Journal of the Korean Recycled Construction Resources Institute
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• v.11 no.1
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• pp.89-96
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• 2023

In this paper, a ferrosilicon by-product was evaluated to confirm the feasibility of recycling it as supplementary cementitious material of ordinary Portland cement in concrete. Three different levels of replacement ratio (10 %, 20 % and 30 % of total binder) were applied to find which is the most beneficial to be used as a binder. Ferrosilicon concrete was initially assessed at setting time and compressive strength. Durability was evaluated by the resistance to chloride penetration test(RCPT) and alkali-silica reaction(ASR) with a comparison to silica fume concrete due to their similarity in chemical composition. The porosimetry and X-ray diffraction analysis along with energy dispersive X-ray spectroscopy give information on the microstructural characteristics of the ferrosilicon concrete. It was found that 10 % ferrosilicon concrete has higher strength while 20 %, 30 % have lower strength than OPC concrete. However, chemical resistance to chloride attack is higher when replacement is increased. Compared to silica fume, the durability of ferrosilicon might be less efficient however, it is obviously beneficial than OPC. High SiO₂ content in ferrosilicon results in producing more C-S-H gel which could make denser pore structure. Most of the risk of alkali silica reaction to silicate binders through length change tests was less than 0.2 %, and both mortar using ferrosilicon and silica fume showed better resistance to alkali silica reaction as the substitution rate increased.Reuse of industrial waste rather than producing highly refined additives might reduce environmental load during manufacture and save costs.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• Journal of Advanced Navigation Technology
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• v.16 no.6
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• pp.1005-1013
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• 2012

In this paper, the induction motor in indirect vector control method modeling, from indirect vector control method it undergoes an influence to the $1/{\tau}$. When changing a rotor resistance because being like this quality Matlab/Simulink where it will make what kind of effect in speed presumption it led proposed control system used microprosser TMS320C31 DSP for high speed processing. The effectiveness of the proposed system is verified by simulation and experimental results. This result shows highly characteristic speed estimation and robust character of load regulation. and the flux which it follows in change of parameter and speed presumption it was under simulation and get the good result which it comes to get it analyzed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.23-30
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• 2006

This paper presents a design of a high-efficiency CMOS DC-DC boost converter using a current-sensing feedback method. High-precision current-sensing circuity is incorporated in order to sense the current flowing in the inductor, which determines the switching scheme of the pulse-width modulation. The external components or large chip area for the frequency compensation can be avoided while maintaining the stable operations of the converter. Various input/output voltage levels can be available through the external resistor strings. The designed DC-DC converter is fabricated in a 0.18-um CMOS technology with a thick-gate oxide option. The converter shows the maximum efficiency over 90% for the output voltage of 3.3V and load current larger than 200mA. The load regulation is 1.15% for the load current change of 100mA.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.4
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• pp.197-203
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• 2014

The technology to predict and prevent an accident of the cable system in power station is required. The techniques of inactivated diagnosis, partial discharge and $tan{\delta}$, have been adopted to diagnoze the operating characteristics of cables, but it is not so easy to find out problems in cables in an inactive state before the cable accident happens. In this paper, we did a research on the 6.6kV high-power cables, installed at Korean Western Power Station Co., Ltd. in order to diagonize the cables, playing a major role at the station. We have developed an equipment to measure an insulation resistance based on the temperature and current of the cable. By installing the system in a power station, we could find abnormal status for evaluation of the lifetime. In the short term, by analyzing the data, we apply the research result to the diagnosis and evaluation of the 6.6kV power cables. In the long run, however, we plan to reduce the cost of the installation and operation of cable systems at power stations.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2017.04a
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• pp.66-66
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• 2017

국내 농촌의 인구고령화, 여성화 증가로 인한 농촌노동력 감소 문제를 해결하기 위해 농업기계자동화에 관한 연구가 활발히 진행되고 있다. 본 연구는 자동화농업기계 중 자동 이식기의 성능평가 기술을 개발하기 위해 수행되었으며 이를 위해 자동 정식기의 핵심부품인 이식호퍼의 결주율, 이식율, 주간간격, 운동궤적 등을 측정할 수 있는 원형토조 실험장치를 개발하였다. 원형토조 실험장치는 원형토조, 이식호퍼 구동장치, 컨트롤러로 구성되어 있으며 이식호퍼의 회전속도(rpm)를 조절하여 주간간격을 조절할 수 있고 초고속 카메라를 이용하여 이식호퍼의 운동궤적을 측정할 수 있다. 이식작물로 고추, 양배추, 브로콜리의 3종류의 육묘를 이용하여 이식호퍼의 회전속도를 20~60 rpm 구간에서 10 rpm 단위로 속도조건변화를 주고 결주율과 이식율을 측정하였다. 이식호퍼 rpm 속도에 따른 주간거리는 190~560 mm로 나타났다. 각 rpm 단수, 작물별 평균 이식율은 고추육묘가 약 97%, 양배추육묘가 약 94%, 브로콜리육묘가 약 95%로 나타났다. 또한 초고속 카메라를 이용하여 측정한 이식호퍼의 운동궤적을 통해 선진사 제품과 대비하여 차이를 보인 것을 확인하였다. 향후 원형토조 실험장치를 이용해 다양한 작물 및 토양조건에서의 실험 및 토양저항 측정장치 개발을 통해 이식작업 진행중에 호퍼에 걸리는 부하에 대한 성능평가시험을 할 계획이다.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2017.04a
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• pp.119-119
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• 2017

부레옥잠은 대량 재배 및 수확이 가능한 수질정화용 식물로 생활하수, 축산폐수, 공장폐수 등의 수질정화 기능이 뛰어나고, 수확물은 건조 및 발효과정을 거쳐 가축 사료, 유기질 비료, 버섯 배지로 사용이 가능하고, 별도의 공업적 처리를 거치면 고부가가치의 바이오 연료, 연소용 연료로 사용이 가능한 친환경 농업 생산물로 본 연구에서는 부레옥잠의 고형연료 제조를 위한 수면에서 수확장치 개발을 위한 견인 특성을 파악하고 장치개발 가능성을 파악하고자 하였다. 부력구조물 부력, 부레옥잠 견인력, 부력을 측정하기 위한 실험 장치를 제작하여 부레옥잠 중량, 견인방식, 견인속도에 따른 견인력을 측정하였고, 경남 거제시에 위치한 저수지에서 실제 견인실험을 수행하였다. 실험결과 견인중량 및 견인 속도가 증가할수록 견인력은 증가하였으며 인력으로 부레옥잠을 견인하는 경우 부레옥잠 중량당 견인력은 약 $0.9{\sim}1.39kg_f$로 나타났으며 이는 향 후 부레옥잠 견인장치를 설계할 경우 부레옥잠 견인중량에 따른 견인력 산정 시 참고 자료로 매우 유용하게 활용 가능할 것으로 판단되었다. 저수지에서 견인실험 결과 견인속도 증가에 따른 유속저항으로 경운기에 의한 견인작업은 불가능하였으며 인력에 위한 견인 실험결과 부레옥잠 단위중량당 견인력은 견인바 3 m의 경우 1.5 ~ 2.6 N/kg, 견인바 6 m의 경우 2.1 ~ 5.4 N/kg로 비교적 크기로 나타났으나, 견인용 바에 따른 요인을 고려한 경우는 0.36 ~ 0.91 N/(kg-m)로 비교적 일정한 값을 보였다. 견인용 바 6 m, 무부하에서 인력과 경운기로 견인하는 경우 견인력은 39.24 N, 153.03 N으로 인력으로 견인하는 경우가 견인력이 작게 측정되었음. 이는 속도증가에 따라 물의 저항력이 증가함으로 나타난 결과로 부레옥잠 견인 시 견인속도는 0.36 m/s가 가장 적합한 것으로 판단되었다.

• 전자공학회논문지 IE
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• v.47 no.2
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• pp.13-20
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• 2010

This paper describes a current mode PWM DC-DC converter IC for battery charger and supply power converter for portable electronic devices. The maximum supply voltage of IC is 40[V] and 2.8[V]~330[V] DC input power is converted to higher or programmed DC voltage according to external resistor ratio or wire winding ratio of transformer. The maximum supply output current is 3[A] over and voltage error of output node is within 3[%]. The whole circuit needed current mode PWM DC-DC converter circuit is designed. The package dimensions and number of external parts are minimized in order to get a smaller hardware size. The power consumption is smaller then 1[mW] at stand by period with supply voltage of 3.6[V] and maximum energy conversion efficiency is about 86[%]. This device has been designed in a 0.6[um] double poly, double metal 40[V] CMOS process and whole chip size is 2100*2000 [um2].

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.6 s.97
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• pp.644-651
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• 2005

In this paper, a new predistortion method to reduce nonlinearity or a traveling wave tube amplifiers(IWTAs) is proposed. Nonlinear transfer characteristics of TWTA are analyzed using carrier complex power series. Inverse carrier complex power series or a predistortion linearizer to linearizer TWTA are also proposed. The inverse nonlinear distortion characteristics of predistorter can be realized with reflective structure that is composed of Schottky diode and resistive-terminated transmission line. The AM-to-AM and the AM-to-PM characteristics for TWTA by proposed predistortive linearizer on K-band were improved from -5.825 dB and -37.321^{\circ} to 0.786 dB and 6.742^{\circ}, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.1
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• pp.69-75
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• 2010

In this paper, with using the clapp type VCO(Voltage Controlled Osillator) configuration a wideband frequency synthesizer in UHF band is proposed. In order to design a wideband frequency synthesizer, the variation of phase in the negative resistance circuit as well as the load circuit was analyzed. Based on this result we propose a method to widen the operation range of the VCO. A frequency synthesizer using the proposed wideband VCO was designed and fabricated. It is shown that the synthesizer has the operating frequency range of 740~1,530 MHz by 0~5 V varactor tuning voltage, and it had the output power of 2~-6 dBm. Moreover, the phase noise measured as -77 dBc/Hz at 10 kHz offset, and as -108 dBc/Hz at 100 kHz offset from the oscillation frequency.