• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.9-16
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• 2008

This paper presents a new Boolean extraction technique for logic synthesis. This method extracts two-cube Boolean subexpression pairs from each logic expression. It begins by creating two-cube array, which is extended and compressed with complements of two-cube Boolean subexpressions. Next, the compressed two-cube array is analyzed to extract common subexpressions for several logic expressions. The method is greedy and extracts the best common subexpression. Experimental results show the improvements in the literal counts over well-known logic synthesis tools for some benchmark circuits.

• Journal of the Korea Computer Industry Society
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• v.7 no.4
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• pp.293-298
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• 2006

A factorization is an extremely important part of multi-level logic synthesis. The number of literals in a factored form is a good estimate of the complexity of a logic function, and can be translated directly into the number of transistors required for implementation. Factored forms are described as either algebraic or Boolean, according to the trade-off between run-time and optimization. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube Boolean subexpression pairs from given expression. Experimental results on various benchmark circuits show the improvements in literal counts over the algebraic factorization based on Bryton's co-kernel cube matrix.

• Journal of the Korea Computer Industry Society
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• v.7 no.5
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• pp.473-480
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• 2006

Extraction is tile most important step in global minimization. Its approache is to identify and extract subexpressions, which are multiple-cubes or single-cubes, common to two or more expressions which can be used to reduce the total number of literals in a Boolean network. Extraction is described as either algebraic or Boolean according to the trade-off between run-time and optimization. Boolean extraction is capable of providing better results, but difficulty in finding common Boolean divisors arises. In this paper, we present a new method for Boolean extraction to remove the difficulty. The key idea is to identify and extract two-cube Boolean subexpression pairs from each expression in a Boolean network. Experimental results show the improvements in the literal counts over the extraction in SIS for some benchmark circuits.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.337-340
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• 2000

In this paper, we put forth a procedure that target low power logic synthesis based on XOR representation of Boolean functions, and the results of synthesis procedure are a multi-level XOR form with minimum switching activity. Specialty, this paper show a method to extract the common cubes or kernels by Boolean matrix and rectangle covering, and to estimate the power consumption in terms of the extracted common sub-functions.

• The Journal of Korean Association of Computer Education
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• v.20 no.4
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• pp.77-84
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• 2017

This paper proposes a tool that can be used as a logical expression simplification tool that can be used for deepening learning of logic circuits and further utilized as a design automation tool for optimizing semiconductor parts. The simplification method of logical expressions proposed in this paper is to find common subexpressions existing in various logical expressions and reduce the repetitive use. Finally, the goal is to minimize the number of literals used in all logical expressions. These previous studies failed to produce a common subexpression embedded in the logical expressions because they only use division principle. The proposed method uses cubes with a Hamming distance of 3 to find the common subexpression embedded between logical expressions. Experiments using benchmark circuits show that the proposed method reduces the number of literals by as much as 47% when comparing simplifications with other methods.

• Journal of Korean Society for Geospatial Information Science
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• v.8 no.2 s.16
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• pp.117-127
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• 2000

The economic development and the development of medical treatment by scientific technology development progressed the level of national people life and improved average life gradually. In this reason, old people who have finance power would like to receive a comport and high level service, though paying proper expense. In this study, receiving this requirement, we focused that silver town have reasonable and comfortable residing environment in developing rural and rest form silver town objecting external area of Chon-Ju city, and selected land suitability. Through the learning of the neural network theory in the method of land suitability, we applied in the full of study area and improved a flexible determination making as giving each class value in each cell. Also, we compare a method of land suitability using the neural network theory, and it's analysis with a method of land suitability by the duplication method of Boolean Logic have been used In Geo Spatial Information System(GSIS) and proved the Boolean Logic's lose of values and the propriety.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.6
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• pp.127-134
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• 2001

At PKC\`98, SangUk Shin et al. proposed a new hash function based on advantages of SHA-1, RIPEMD-160, and HAVAL. They claimed that the Boolean functions of the hash function have good properties including the SAC(Strict Avalanche Criterion). In this paper, we first show that some of Boolean functions which are used in Shin\`s hash function does not satisfy the SAC, and then argue that satisfying the SAC may not be a good property of Boolean functions, when it is used for constructing compress functions of a hash function.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.6 no.3
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• pp.31-40
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• 1996

In [4, 12], Chee et al. proposed a new class of cryptographic primitive, 'semi-bent functions', which exists on only odd dimensional vector spaces [4]. In this paper, we discuss new notion of generalized semi-bent functions which can be defined on any vector spaces. And we suggest systematic methods for constructing generalized semi-bent functions and analyse their cryptographic properties. In addition, we show that SUC fulfilling Boolean functions can be found on any dimensional vector spaces.

• Korean Journal of Cognitive Science
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• v.17 no.4
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• pp.303-321
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• 2006

According to Harris'(1966) distributional hypothesis, understanding the meaning of a word is thought to be dependent on its context. Under this hypothesis about human language ability, this paper proposes a computational model for native speaker's language processing mechanism concerning word sense disambiguation, based on two sets of experiments. Among the three computational models discussed in this paper, namely, the logic model, the probabilistic model, and the probabilistic inference model, the experiment shows that the logic model is first applied fer semantic disambiguation of the key word. Nexr, if the logic model fails to apply, then the probabilistic model becomes most relevant. The three models were also compared with the test results in terms of Pearson correlation coefficient value. It turns out that the logic model best explains the human decision behaviour on the ambiguous words, and the probabilistic inference model tomes next. The experiment consists of two pans; one involves 30 sentences extracted from 1 million graphic-word corpus, and the result shows the agreement rate anong native speakers is at 98% in terms of word sense disambiguation. The other pm of the experiment, which was designed to exclude the logic model effect, is composed of 50 cleft sentences.

• Journal of the Korea Society of Computer and Information
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• v.10 no.3 s.35
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• pp.11-18
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• 2005

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint. This algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by $62.2\%$ than those of DDMAP. And reduced the number of CLBs by $17.6\%$ than those of TEMPLA.