• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.5
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• pp.31-37
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• 2009

In the two-way relay channel, the relay employ Amplify-and-Forward (AF) or Decode-and-Forward (DF) protocol, and broadcast the network-coded signal to both user. In the system, DF protocol provides maximum throughput at low signal to noise ratio(SNR). On the other hand, at high SNR, AF protocol provides maximum throughput. The paper propose active transmission scheme which employ Amplify-and-Forward or Decode-and-Forward protocol based on received SNR at the relay over Two-way relay channel. The optimal threshold is investigated numerically for switching the protocol. Through numerical results, we confirm that the proposed scheme outperforms conventional schemes over two-way relay channel.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.63-70
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• 2016

To increase throughput efficiency and improve performance, FTN(Faster Than Nyquist) method and LDPC(Low Density Parity Code) codes are employed in DVB-S3 system. In this paper, we proposed efficient turbo equalization model to minimize inter symbol interference induced by FTN transmission. This paper introduces two conventional scheme employing SIC(Successive Interference Cancellation) and BCJR equalizer. Then, we proposed new scheme to resolve problems in this two conventional scheme. To make performance improved in turbo equalization model, the outputs of LDPC and BCJR equalizer are iteratively exchange probabilistic information. In fed LDPC outputs as extrinsic informa tion of BCJR equalizer. we split LDPC output to separate bit probabilities. We compare performance of proposed scheme to that of conventional methods through using simulation in AWGN(Additive White Gaussian Noise) channel. We confirmed that performance was improved compared to conventional methods as increasing throughput parameters of FTN.

• The Journal of the Acoustical Society of Korea
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• v.34 no.4
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• pp.295-302
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• 2015

Acoustic channels are characterized by long multipath spreads that cause inter-symbol interference. The way in which this fact influences the design of the receiver structure is considered. To satisfy performance and throughput, we presented consecutive iterative BCJR (Bahl, Cocke, Jelinek, Raviv) equalization to improve the performance and throughput. To achieve low error performance, we resort to powerful BCJR equalization algorithms that iteratively update probabilistic information between inner decoder and outer decoder. Also, to achieve high throughput, we divide long packet into consecutive small packets, and the estimate channel information of previous packets are compensated to next packets. Based on experimental channel response, we confirmed that the performance is improved for long length packet size.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.22-30
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• 2011

In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys' Design Compiler using Chartered $0.18{\mu}m$ CMOS cell library. The synthesized design has the gate size of 455K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1248-1255
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• 2012

LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies horizontal shuffle scheduling(HSS) algorithm and self-correction normalized min-sum(SC-NMS) algorithm. In the result, number of iteration is half than conventional algorithm and performance is almost same between sum-product(SP) and SC-NMS. Finally, This paper implements high-speed LDPC decoder based on FPGA. Decoding throughput is 816 Mbps.

• The Journal of the Korea Contents Association
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• v.16 no.3
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• pp.91-101
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• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.78-89
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• 2013

This paper proposes a high-throughput and multi-mode quasi-cyclic (QC) low-density parity-check (LDPC) decoder based on a fully parallel structure. The proposed QC-LDPC decoder employs the fully parallel structure to provide very high throughput. The high interconnection complexity, which is the general problem in the fully parallel structure, is solved by using a broadcasting-based sum-product algorithm and proposing a low-complexity cyclic shift network. The high complexity problem, which is caused by using a large amount of check node processors and variable node processors, is solved by proposing a combined check and variable node processor (CCVP). The proposed QC-LDPC decoder can support the multi-mode decoding by proposing a routing-based interconnection network, the flexible CCVP and the flexible cyclic shift network. The proposed QC-LDPC decoder is operated at 100 MHz clock frequency. The proposed QC-LDPC decoder supports multi-mode decoding and provides 8.1 Gbps throughput for a (1944, 1620) QC-LDPC code.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.3
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• pp.311-317
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• 2013

In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard for applying marine communications in order to multimedia transmission. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed partial memory structure in order to reduced the delay and high speed decoder is possible. The results of the simulation, when the max number of iteration set to 30 times, decoding throughput of HSS algorithm is 326 Mbit/s and decoding speed of proposed algorithm is 2.29 Gbit/s. So, decoding speed of proposed algorithm more than 7 times could be obtained compared to the HSS algorithm.

• Journal of Navigation and Port Research
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• v.38 no.3
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• pp.211-216
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• 2014

In this paper, high throughput method is studied to provide floating objects with broadband service as ship by using satellite. In recent, satellite broadcastings standard is based on DVB-S3 for communication service using wireless device on navigation communication by satellite. LDPC codes are iterative coding algorithm proposed in DVB-S3. In this paper, FTN technique is applied to LDPC codes with 8-PSK modulation and then present the method to alleviate performance degradation due to FTN through BICM-ID. BICM-ID is the method to improve performance by calculating a new LLR from hard-decision value of decoder output. DVB-S2 system with 8-PSK modulation and FTN technique based on iterative decoding had a better performance than DVB-S2 with 8-PSK modulation and FTN technique over Gaussian channels.

• Journal of Advanced Marine Engineering and Technology
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• v.40 no.6
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• pp.535-541
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• 2016

In this paper, we analyzed efficient decoding scheme with FTN(Faster than Nyquist) method that is transmission method faster than Nyquist theory and increase the throughput. Applying the FTN method to satellite and underwater communication, we proposed an efficient transceiver model. To minimize ISI(Inter-Symbol Interference) induced by FTN signal, turbo equalization algorithms that iteratively exchange probabilistic information between Viterbi equalizer based on BCJR algorithm and LDPC decoder are used in satellite communication. In others, for underwater communication, DFE equalizer and LDPC decoder are concatenated to improve performance.