• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• Journal of Broadcast Engineering
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• v.14 no.2
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• pp.134-143
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• 2009

In this paper, we propose a new relay selection algorithm for a two-way multiple relay channel. In the two-way multiple relay channel, two users exchange information with each other via multiple relays. The relays use a decode-and-forward or amplify-and-forward protocol, and exploit the combining process of the received packets to reduce the required channel resources. In the multiple relay network, diversity gain is achieved as the number of relays increases, and various schemes are proposed. In this paper, we propose a single best relay selection scheme based on instantaneous channel conditions. First of all, relays obtain the instantaneous channel state information in the handshaking process, and a single best relay is selected in a distributed methods prior to data transmissions. The relay selection metric is proposed so that the end-to-end channel condition is evaluated based on the intantaneous channel state informations. Simulation results show that the proposed relay selection algorithm achieve the increased throughput and diversity order when the number of potential relays is increased.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.5
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• pp.17-30
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• 2001

In this paper, we implemented a scalar multiplier needed at an elliptic curve cryptosystem over standard basis in $GF(2^{163})$. The scalar multiplier consists of a radix-16 finite field serial multiplier and a finite field inverter with some control logics. The main contribution is to develop a new fast finite field inverter, which made it possible to avoid time consuming iterations of finite field multiplication. We used an algorithmic transformation technique to obtain a data-independent computational structure of the Extended Euclid GCD algorithm. The finite field multiplier and inverter shown in this paper have regular structure so that they can be easily extended to larger word size. Moreover they can achieve 100% throughput using the pipelining. Our new scalar multiplier is synthesized using Hyundai Electronics 0.6$\mu\textrm{m}$ CMOS library, and maximum operating frequency is estimated about 140MHz. The resulting data processing performance is 64Kbps, that is it takes 2.53ms to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption & decryption and key exchange in real time embedded-processor environments.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.9-16
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• 2013

Long term evolution (LTE) and LTE-Advanced (LTE-A) systems adopt closed-loop multiple-input multiple-output antenna techniques. Equal gain transmission which has equal gain property is the key factor in their codebook design. In this paper, a novel differential codebook structure which maintains the codebook design requirements of LTE or LTE-A systems. Especially, eight-phase shift keying (8-PSK) constellations are used as elements of codewords, which not only maintain equal gain property but also reduce the computation complexity of precoding and decoding function blocks. The equal gain property is very important to uplink because the performance of uplink is very sensitive to the peak-to-average power ratio (PAPR). Moreover, the operation of the proposed differential codebook is explained as a rotation-lock structure. As the results of computer simulations, the steady-state throughput performance of the proposed codebook shows at least 0.9dB of SNR better than those of the conventional LTE codebook with the same amount of feedback information.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.6A
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• pp.592-600
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• 2011

This paper presents a selective interference alignment for cognitive radio system with spectrum leasing. The proposed method selects users who cause severe interference to other basestations that have required SINR. Since few users are selected to apply subspace interference alignment, the total complexity of the system is not high compared with that of the system who utilizes subspace interference alignment to all users. In addition, all users can transmit without considering interference. The computer simulation shows the proposed method exhibits 350% throughput enhancement at a two cell case, and 400% increase at a three cell case.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.125-128
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• 2011

This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8A
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• pp.640-647
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• 2009

IEEE 802.11i is an amendment to the original IEEE 802.11/b,a,g standard specifying security mechanism by stipulating RSNA for tighter security. The RSNA uses TKIP(Temporal Key Integrity Protocol) and CCMP(Counter with CBC-MAC Protocol) instead of old-fashioned WEP(Wired Equivalent Privacy) for data encryption. This paper describes a design of a communication security engine for IEEE 802.11i MAC layer. The design includes WEP and TKIP modules based on the RC4 encryption algorithm, and CCMP module based on the AES encryption algorism. The WEP module suffices for compatibility with the IEEE 802.11 b,a,g MAC layer. The CCMP module has about 816.7Mbps throughput at 134MHz, hence it satisfies maximum 600Mbps data rate described in the IEEE 802.11n specifications. We propose a pipelined AES-CCMP cipher core architecture, which has lower hardware cost than existing AES cores, because CBC mode and CTR mode operate at the same time.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.4
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• pp.1-9
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• 2008

This paper presents a rapid watermarking algorithm based on DC image, which provides a resilience to geometric distortion. Our proposed scheme is based on $8{\times}8$ block DCT that is widely used in image/video compression techniques (e.g., JPEG and MPEG). In particular, a DC image is analyzed by DWT to embed a watermark. To overcome a quality degradation caused by a watermark insertion into DC components, we discern carefully the intensity and amount of watermark along the different subbands of DWT. Note that the proposed technique supports a high throughput for a real-time watermark insertion and extraction by relying on a partial decoding (i.e., DC components) on $8{\times}8$ block DCT domain. Experimental result shows that the proposed watermarking scheme significantly reduces computation time of 82% compared with existing DC component based algorithm and yet provides invariant properties against various attacks such as geometric distortion and JPEG compression, etc.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.351-358
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• 2016

This paper describes an efficient hardware implementation of lightweight block cipher algorithm CLEFIA. The CLEFIA crypto-processor supports for three master key lengths of 128/192/256-bit, and it is based on the modified generalized Feistel network (GFN). To minimize hardware complexity, a unified processing unit with 8 bits data-path is designed for implementing GFN that computes intermediate keys to be used in round key scheduling, as well as carries out round transformation. The GFN block in our design is reconfigured not only for performing 4-branch GFN used for round transformation and intermediate round key generation of 128-bit, but also for performing 8-branch GFN used for intermediate round key generation of 256-bit. The CLEFIA crypto-processor designed in Verilog HDL was verified by using Virtex5 XC5VSX50T FPGA device. The estimated throughput is 81.5 ~ 60 Mbps with 112 MHz clock frequency.