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40Gb/s Foward Error Correction Architecture for Optical Communication System  

Lee, Seung-Beom (School of Information and Communication Engineering, Inha University)
Lee, Han-Ho (School of Information and Communication Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.2, 2008 , pp. 101-111 More about this Journal
Abstract
This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.
Keywords
Error correction coding; area-efficient; Reed-Solomon decoder; fiber optic; communications;
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