• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.344-352
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• 2020

Covertness and performance are very important design goals in the underwater communications. To satisfy both of them, we proposed efficient underwater communication model which combined multiband and direct sequence spread spectrum method in order to improve performance and covertness simultaneously. Turbo coding method with 1/3 coding rates is used for channel coding algorithm, and turbo equalization method which iterately exchange probabilistic information between equalizer and decoder is used for receiver side. After optimal threshold value was set in Rake processing, this paper analyzed the performance by varying the number of chips were 8, 16, 32 and the number of bands were from 1 to 4. Through the simulation results, we confirmed that the performance improvement was obtained by increasing the number of bands and chips. 2~3 dB of performance gain was obtained when the number of chips were increased in same number of bands.

• The Transactions of the Korea Information Processing Society
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• v.6 no.12
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• pp.3597-3605
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• 1999

We introduce a new satellite Conditional Access System(CAS) that a subscriber could watch a pay-TV knowing only his or her identity and password, without using a smart card. For this new system, two password-based protocols are presented which not only share a session key and authenticate each other but also download an authorization key. This system has some merits: First, compared with current systems, it reduces the amount of computations by eliminating the AK-encryption module in SMS(Subscriber Management System) and simplifying the receiver's CW-decryption process. Second, since this system does not need an expensive Card Adaptive Device(CAD), it can reduce costs. finally it provides descrambler independence allowing it to be used through any TV set-top box that includes a descrambler, unlike the current system that a descrambler is linked with a smart card.

• Journal of Internet Computing and Services
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• v.17 no.6
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• pp.9-15
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• 2016

In this paper, we propose a smart HLS(HTTP Live Stream) platform with dynamic single buffering for the best transmission of adaptive video bit-rates. This smart HLS can optimizes the channel transition zapping-time with the monitoring of bandwidth between HLS server and OTT(Over The Top) client. This platform is designed through the control of video stream due to proper multi-bitrates and bandwidths. This proposed OTT can decode the live and VOD(Video On Demand) videos with the buffering of optimumal bitrate. And, the HLS can be cooperated with a smart OTT, and segmented for the m3u8 files of H.265 MPEG-2 TS(Transport Stream) videos. As a resullt, this single buffer based smart OTT can transmit optimal videos with the maximum data buffering according to the adaptive bit-rate depending on the network bandwidth efficiency and the decoded VOD video, too.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.5
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• pp.430-437
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• 2021

In this paper, we propose a robust face recognition method against soft errors with a deep convolutional generative adversarial network(DCGAN) based compensation method by a cross-layer approach. When soft-errors occur in block data of JPEG files, these blocks can be decoded inappropriately. In previous results, these blocks have been replaced using a mean face, thereby improving recognition ratio to a certain degree. This paper uses a DCGAN-based compensation approach to extend the previous results. When soft errors are detected in an embedded system layer using parity bit checkers, they are compensated in the application layer using compensated block data by a DCGAN-based compensation method. Regarding soft errors and block data loss in facial images, a DCGAN architecture is redesigned to compensate for the block data loss. Simulation results show that the proposed method effectively compensates for performance degradation due to soft errors.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.6
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• pp.15-24
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• 2006

Recently, the importance of the area efficient implementation of cryptographic algorithm for the portable device is increasing. Previous ARIA(Academy, Research Institute, Agency) implementation styles that usually concentrate upon speed, we not suitable for mobile devices in area and power aspects. Thus in this paper, we present an area efficient AR processor which use 32-bit architecture. Using new implementation technique of diffusion layer, the proposed processor has 11301 gates chip area. For 128-bit master key, the ARIA processor needs 87 clock cycles to generate initial round keys, n8 clock cycles to encrypt, and 256 clock cycles to decrypt a 128-bit block of data. Also the processor supports 192-bit and 256-bit master keys. These performances are 7% in area and 13% in speed improved results from previous cases.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.4
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• pp.21-28
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• 2009

In the recent years, power attacks were widely investigated, and so various countermeasures have been proposed, In the case of block ciphers, masking methods that blind the intermediate values in the algorithm computations(encryption, decryption, and key-schedule) are well-known among these countermeasures. But the cost of non-linear part is extremely high in the masking method of block cipher, and so the inversion of S-box is the most significant part in the case of AES. This fact make various countermeasures be proposed for reducing the cost of masking inversion and Zakeri's method using normal bases over the composite field is known to be most efficient algorithm among these masking method. We rearrange the masking inversion operation over the composite field and so can find duplicated multiplications. Because of these duplicated multiplications, our method can reduce about 10.5% gates in comparison with Zakeri's method.

• Korean Journal of Optics and Photonics
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• v.17 no.3
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• pp.248-255
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• 2006

Most optical security systems use a 4-f correlator, Mach-Zehnder interferometer, or a joint transform correlator(JTC). Of them, the JTC does not require an accurate optical alignment and has a good potential for real-time processing. In this paper, we propose an image encryption system using a position shift property of the JTC in the Fourier domain and a random phase image. Our encryption system uses two keys: one key is a random phase mask and the other key is a position shift factor. By using two keys, the proposed method can increase the security level of the encryption system. An encrypted image is produced by the Fourier transform for the multiplication image, which resulted from adding position shift functions to an original image, with a random phase mask. The random phase mask and position shift value are used as keys in decryption, simultaneously. For the decryption, both the encrypted image and the key image should be correctly located on the JTC. If the incorrect position shift value or the incorrect key image is used in decryption, the original information can not be obtained. To demonstrate the efficiency of the proposed system, computer simulation is performed. By analyzing the simulation results in the case of blocking of the encrypted image and affecting of the phase noise, we confirmed that the proposed method has a good tolerance to data loss. These results show that our system is very useful for the optical certification system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.64-70
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• 2008

The H.264 standard is widely used due to the high compression rate and quality. The deblocking filter of the H.264 standard improves the quality of images by eliminating blocking artifacts of pictures, and it requires a lot of computation. We propose a new hardware architecture for the deblocking filter with pipelined architecture, 1-D filters which support both horizontal and vertical filtering and efficient memory management. Four memory blocks are configured for the efficient storage and access of the current macroblock and adjacent referenced sub-macroblocks, and the pixel data from the motion compensation unit can be transferred without waiting during the computation cycles of the deblocking filter. The number of computation cycles and the hardware area are reduced using the proposed architecture, and the performance of the H.264 decoder is improved. We design the deblocking filter using Verilog-HDL and implement using an FPGA. The designed deblocking filter can be used for decoding HD quality images at 77 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.100-108
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• 2018

This paper describes a design of scalable RSA public-key cryptography processor supporting four key lengths of 512/1,024/2,048/3,072 bits. The modular multiplier that is a core arithmetic block for RSA crypto-system was designed with 32-bit datapath, which is based on the CIOS (Coarsely Integrated Operand Scanning) Montgomery modular multiplication algorithm. The modular exponentiation was implemented by using L-R binary exponentiation algorithm. The scalable RSA crypto-processor was verified by FPGA implementation using Virtex-5 device, and it takes 456,051/3,496347/26,011,947/88,112,770 clock cycles for RSA computation for the key lengths of 512/1,024/2,048/3,072 bits. The RSA crypto-processor synthesized with a $0.18{\mu}m$ CMOS cell library occupies 10,672 gate equivalent (GE) and a memory bank of $6{\times}3,072$ bits. The estimated maximum clock frequency is 147 MHz, and the RSA decryption takes 3.1/23.8/177/599.4 msec for key lengths of 512/1,024/2,048/3,072 bits.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.4
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• pp.819-826
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• 2018

The generalized Hamming weight is one of the important parameters of the linear code. It determines the performance of the code when the linear codes are applied to a cryptographic system. In addition, when the block code is decoded by soft decision using the lattice diagram, it becomes a measure for evaluating the state complexity required for the implementation. In particular, a bit-parallel multiplier on finite fields based on trinomials have been studied. Cellular automata(CA) has superior randomness over LFSR due to its ability to update its state simultaneously by local interaction. In this paper, we deal with the efficient synthesis of the pseudo random number generator, which is one of the important factors in the design of effective cryptosystem. We analyze the property of the characteristic polynomial of the simple 90/150 transition rule block, and propose a synthesis algorithm of the reversible 90/150 CA corresponding to the trinomials $x^2^n+x^{2^n-1}+1$($n{\geq}2$) and the 90/150 reversible CA(RCA) corresponding to the maximum weight polynomial with $2^n$ degree by using this rule block.