• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.5
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• pp.409-416
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• 2017

In this paper, we consider a framework of compressed sensing over finite fields. One measurement sample is obtained by an inner product of a row of a sensing matrix and a sparse signal vector. A recovery algorithm proposed in this study for sparse signals based probabilistic decoding is used to find a solution of compressed sensing. Until now compressed sensing theory has dealt with real-valued or complex-valued systems, but for the processing of the original real or complex signals, the loss of the information occurs from the discretization. The motivation of this work can be found in efforts to solve inverse problems for discrete signals. The framework proposed in this paper uses a parity-check matrix of low-density parity-check (LDPC) codes developed in coding theory as a sensing matrix. We develop a stochastic algorithm to reconstruct sparse signals over finite field. Unlike LDPC decoding, which is published in existing coding theory, we design an iterative algorithm using probability distribution of sparse signals. Through the proposed recovery algorithm, we achieve better reconstruction performance as the size of finite fields increases. Since the sensing matrix of compressed sensing shows good performance even in the low density matrix such as the parity-check matrix, it is expected to be actively used in applications considering discrete signals.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.

• The Transactions of the Korean Institute of Power Electronics
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• v.7 no.2
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• pp.205-213
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• 2002

This paper deals with the implementation of three-phase VSI systems which can control the power regenerated from DC bus line to AC supply. The overall system consists of the line-to-line voltage and line current sensors, an actual power calculator using d-q transformation method, a complex power controller with PI control scheme, a gating signal generator for modified ｑ-conduction mode, a DPLL for frequency followup, and Power circuits. Control board is constructed by using a 32-bit DSP TMS32C32, two EFLDs , six ADCs, and a DAC. To verify the performance of the proposed system, we designed and constructed the propotype with the power rating of 5kVA at AC 220V. Experimental results show that the regenerated active power is well controlled to its command vague and the regenerated reactive power still remained at nearly zero through all operating modes.

• The Journal of the Acoustical Society of Korea
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• v.23 no.1
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• pp.17-23
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• 2004

The mobile radio channel can be simulated as a complex-valued random process with narrow-band spectrum. This paper describes a real-time implementation of that process using a INS320C6414 digital signal processor and XC2VP30 Virtex FPGA. The simulator presented here is not only a comprehensive model of the flat fading but also frequency selective fading mobile channel conditions. To replicate the statistical characteristics of the multipath fading environment with the minimum computational burden, multi-rate techniques are employed to resolve practical problems such as variable sampling rate. The simulator produces accurate and consistent results due to digital implementation. It is very flexible and simple to program for various field conditions in mobile communications with a graphical user interface.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.65-73
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• 2002

In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 1995.10a
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• pp.289-295
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• 1995

구조물의 동적부하에 대한 동적변형 응답을 정확히 예측하고, Over Design이나 Under Design이 아닌 합리적인 설계방안의 개발은 중요한 과제이다. 동적강도해석이나 소음 승차감과 같은 진동 및 충격에 기인하는 제반 문제를 복잡한 구조물을 대상으로 합리적으로 처리하기 위한 Dynamic Design Analysis는 높은 신뢰성의 추구와 더불어 필요불가결한 기술이 되고 있다. 동적해석 방법으로는 현재 유한요소법이 널리 사용되고 있으며 여러 종류의 범용 프로그램들이 보급되어 있는 실정이다. 그러나 특히 동적문제에 있어서는 형상이나 거동이 복잡한 구조물의 경우, 또는 차량의 차체와 같이 많은 장착물이 부착된 경우에는 유한요소법의 적용이 곤란하여, 지금까지 대처할 수 있는 유용한 방법이 없었다. 따라서 비교적 용이하고 간단하게 적용가능한 진동실험을 기초로 한 구조물의 동적 응답해석 및 설계 방안의 개발이 필요하다. 본 연구에서는 진동시험으로 얻어진 부분구조물의 응답특성과 결합특성으로부터 결합 후의 응답특성을 예측할 수 있는 방법을 전달함수합성이론을 기초로하여 프로그래밍 package화 한다. 그리고 평판구조물에 대하여 진동시험과 컴퓨터 시뮬레이션을 통하여 개발된 방법의 타당성을 검증한다. 또한 실제 차량에서 차체만의 진동시험과 엔진의 자유진동시험에 의한 시험데이터로부터 차체와 엔진이 마운트 결합된 후의 진동특성을 예측한다. 진동시험시에 입력과 출력에 노이즈가 필연적으로 혼입되어 주파수응답함수의 크기(magnitude)와 위상(phase)을 왜곡시킨다. 특히 위상의 왜곡은 복소수연산을 하는 전달함수합성법의 결과에 중요한 영향을 미치게 된다. 본 연구에서는 데이타 획득시 입력과 출력의 시간지연으로 생기는 위상왜곡을 보정하는 방법을 제시하고, 그 개선 정도를 조사한다.는 소견의 확실도로서 가능성을 표현한 것이다. 예를 들면, 진동진폭 스펙트럼상에 2X 성분이 상당히 크게 나타나 정렬불량의 가능성이 0.7 정도라고 판정하는 것 등은 이러한 수치적진리치를 이용하는 방법이다. 그러나 상기의 수치적 표현만으로는 확실도를 한개의 수치로서 대표하게 하는 것은 진단의 정밀도에 문제가 있을 것으로 생각된다. 따라서 언어적진리치가 도입되어 [상당히 확실], [확실], [약간 확실] 등의 언어적인 표현을 이용하여 애매성을 표현하게 되었다. 본 논문에서는 간이진단 결과로부터 추출된 애매한 진단결과중에서 가장 가능성이 높은 이상원인을 복수로 선정하고, 여러 종류의 수치화할 수 없는 언어적(linguistic)인 정보ㄷㄹ을 if-then 형식의 퍼지추론으로 종합하는 회전기계의 이상진단을 위한 정밀진단 알고리즘을 제안하고 그 유용성을 검토한다. 존재하여도 모우드 변수들을 항상 정확하게 구할 수 있으며, 또한 알고리즘의 안정성이 보장된 것이다.. 여기서는 실험실 수준의 평 판모델을 제작하고 실제 현장에서 이루어질 수 있는 진동제어 구조물에 대 한 동적실험 및 FRS를 수행하는 과정과 동일하게 따름으로써 실제 발생할 수 있는 오차나 error를 실험실내의 차원에서 파악하여 진동원을 있는 구조 물에 대한 진동제어기술을 보유하고자 한다. 이용한 해마의 부피측정은 해마경화증 환자의 진단에 있어 육안적인 MR 진단이 어려운 제한된 경우에만 실제적 도움을 줄 수 있는 보조적인 방법으로 생각된다.ofile whereas relaxivity at high field is not affected by τS. On the other hand, the change in τV does not affect low field profile but strongly in fluences on bot

• Korean Journal of Optics and Photonics
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• v.24 no.5
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• pp.245-250
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• 2013

The Wiener-Khinchin theorem, which means that the autocorrelation function of a signal corresponds to the power spectrum of the signal, is very important in signal processing, spectroscopy and telecommunications engineering. However, because of needs for some relatively expensive equipments such as a correlator and the signal processing system, its demonstration in most undergraduate class is not easy so far. Recently, digital oscilloscopes whose functions can be replaced foresaid equipments are marketed with development of digital engineering. In this paper, a simple demonstration of the theorem is given by a digital storage oscilloscope and a personal computer with its theoretical background. The reason that deals again with this theorem which has been introduced in 1930 is that it has been not well informed yet to us and theoretical background of the demonstration is directly introduced from its driving process. Through deriving process of the theorem, some extended physical meanings of the impedance, power, power factor, Wiener spectrum, linear system response and, furthermore, basic idea of the Planck's quantization in the black body theory reveal themselves naturally. Hence it can be referred to lectures in general physics, modern physics, spectroscopy and material characterization experiment.