• Journal for History of Mathematics
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• v.20 no.3
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• pp.59-72
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• 2007

In this paper we find the germ of geometric interpretation of complex number in the Euclid Element and try to show the evolution of geometric interpretation of complex number by through Descarte, Wallis, Vessel. As a result, relations and differences between them are found. They related line with complex number and interpreted complex number geometrically by generalizing the multiplication operation.

• Journal of Educational Research in Mathematics
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• v.18 no.1
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• pp.51-62
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• 2008

In the 7th-curriculum, only basic arithmetics of complex numbers have been taught. They are taught formally like literal manipulations. This paper analyzes mathematically essential relations between algebra of complex numbers and plane geometry. Historical analysis is also performed to find effective methods of teaching complex numbers in school mathematics. As a result, we can integrates this analysis with school mathematics by help of Viete's operations on right triangles. We conclude that teaching geometric interpretation of complex numbers is possible in school mathematics.

• School Mathematics
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• v.10 no.3
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• pp.357-374
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• 2008

The complex number system is supposed to introduce first chapter in the first grade of high school. When number system is expanded to complex numbers, the main aim is to understand preservation of algebraic structure with regard to the flow of curriculum and textbook. This research reviewed overall alternative articulation and treatment of textbooks from a logical viewpoint. Two research questions are developed below. First, in the structure of the current curriculum, when we consider student's 'level', how are the alternative articulation and treatment of textbooks in complex unit on a logical point of view? Second, What are more logical alternative articulation and treatment? What alternative articulation and treatment are suitable for a running goal? and what are the improvement which is definitive?

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.123-130
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• 2016

In this paper, a high-performance arithmetic unit which can efficiently accelerate a number of algorithms for multimedia application was designed. The 3-stage pipelined arithmetic unit can execute 38 operations for complex and fixed-point data by using efficient configuration for four 16-bit by 16-bit multipliers, new sign extension method for carry-save data, and correction constant scheme to eliminate sign-extension in compression operation of multiple partial multiplication results. The arithmetic unit has about 300-MHz operating frequency and about 37,000 gates on 45nm CMOS technology and its estimated performance is 300 MCOPS(Million Complex Operations Per Second). Because the arithmetic unit has high processing rate and supports a number of operations dedicated to various applications, it can be efficiently applicable to multimedia processors.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.73-76
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• 2003

본 논문에서는 MPEG-2 BC와 AAC의 복호화 과정 중 함성 필터링 과정의 알고리듬을 분석하여 공동된 구조로 연산을 수행한 수 있는 광용 합성 필터 구조에 대하여 논하였다. 제안된 공용 합성 필터 구조는 Regressive 구조를 이용하여 MPEG-2 BC와 AAC의 복호화를 효과적으로 공용 수행하도록 하였다. 제안한 구조는 FFT를 사용할 경우에 필요한 전처리 및 후처리 과정을 고려해주지 않아도 되고 복소수 연산이 아닌 실수연산이 되어 하드웨어 구조가 단순하게 된다. 또한 MPEG-2 AAC의 다양한 윈도우 변환에도 안정적으로 연산되는 구조임을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10B
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• pp.1482-1490
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• 2001

디지털 통신 시스템 및 신호처리 회로의 핵심 연산블록으로 사용될 수 있는 복소수 승산기 코어의 파라미터화된 소프트 IP (Intellectual Property)를 설계하였다. 승산기는 응용분야에 따라 요구되는 비트 수가 매우 다양하므로, 승산기 코어 IP는 비트 수를 파라미터화하여 설계하는 것이 필요하다. 본 논문에서는 복소수 승산기의 비트 수를 파라미터화 함으로써 사용자의 필요에 따라 승수와 피승수를 8-b∼24-b 범위에서 2-b 단위로 선택하여 사용할 수 있도록 하였으며, GUI 환경의 코어 생성기 PCMUL_GEN는 지정된 비트 크기를 갖는 복소수 승산기의 VHDL 모델을 생성한다. 복소수 승산기 코어 IP는 redundant binary (RB) 수치계와 본 논문에서 제안하는 새로운 radix-4 Booth 인코딩/디코딩 회로를 적용하여 설계되었으며, 이를 통해 기존의 방식보다 단순화된 내부 구조와 고속/저전력 특성을 갖는다. 설계된 IP는 Xilinx FPGA로 구현하여 기능을 검증하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2A
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• pp.188-194
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• 2007

In order to become ubiquitous world, the compatibility of wireless machines has become the significant characteristic of a communication terminal. Thus, SDR is the most necessary technology and standard. However, among the environment which has different communication protocol, it's difficult to make a terminal with only hardware using ASIC or SoC. This paper suggests the processor that can accelerate several communication protocol. It can be connected with main-processor, and it is specialized PHY layer of network The C-program that is modeled with the wireless protocol IEEE802.11a and IEEE802.11b which are based on widely used modulation way; OFDM and CDM is compiled with ARM cross compiler and done simulation and profiling with Simplescalar-Arm version. The result of profiling, most operations were Viterbi operations and complex floating point operations. According to this result we suggested a co-processor which can accelerate Viterbi operations and complex floating point operations and added instructions. These instructions are simulated with Simplescalar-Arm version. The result of this simulation, comparing with computing only one ARM core, the operations of Viterbi improved as fast as 4.5 times. And the operations of complex floating point improved as fast as twice. The operations of IEEE802.11a are 3 times faster, and the operations of IEEE802.11b are 1.5 times faster.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.1940-1943
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• 2003

본 논문은 Polynomial 변환을 이용하여 2차원 Discrete Cosine Transform (2D-DCT)의 계산을 1차원 DCT로 변환하여 계산하는 알고리즘을 개발한다. 기존의 일반적인 알고리즘인 row-column이 N×M의 2D-DCT에서 3/2NMlog₂(NM)-2NM＋N＋M의 합과 1/2NMlog₂(NM)의 곱셈이 필요한데 비하여 본 논문에서 제시한 알고리즘은 3/2NMlog₂M ＋NMlog₂N-M-N/2＋2의 합과 1/2NMlog₂M의 곱셈 수를 필요로 한다. 기존의 polynomial 변환에 의한 2D DCT는 Euler 공식을 적용하였기 때문에 복소 연산이 필요하지만 본 논문에서 제시한 polynomial 변환은 DCT의 modular 규칙을 이용하여 2D DCT를 ID DCT의 합으로 직접 변환하므로 복소 연산이 필요하지 않다. 또한 본 논문에서 제시한 알고리즘은 각 차원에서 데이터 크기가 다른 임의 크기의 2차원 데이터 변환에도 적용할 수 있다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.7
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• pp.47-53
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• 2004

In this paper we introduce a complex escalator (ESC) structure-Equalizer and investigate its performance in complex channels in QPSK undulation systems. The proposed complex equalizer has the complete orthogonalization property and is independent of eigenvalue spread ratio (ESR) of channel. The proposed complex ESC equalizer shows as 7 times faster convergence speed as that of the conventional complex TDL equalizer algorithms in a complex channel model for QPSK systems.