• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.8
• /
• pp.582-594
• /
• 2016

Most studies on hybrid buses are on large-sized buses and not mid-sized low-floor buses. This study uses MATLAB simulation to evaluate the fuel efficiency of such buses powered by diesel. Based on the results, a hybrid electric vehicle system is recommended for the best combination of power and gear ratio. A parallel hybrid system was selected for the hybridization, which transmits front and rear wheel power independently. The necessary power to satisfy the target performance was calculated, and the applicable capacity area was designed. Dynamic programing was used to create and optimize a component sizing algorithm, which was used to scale the capacity of each component of the power source to satisfy the design criteria. The fuel efficiency rate, optimum power source capacity, and gear ratio can be improved by converting a conventional bus into a parallel hybrid bus.

• Journal of The Korean Association For Science Education
• /
• v.34 no.2
• /
• pp.55-62
• /
• 2014

This study is to reclassify the classifications or definitions of scientific literacy in scientific literacy researches since 1960s and grasp the classification trends of scientific literacy definitions. Sixteen articles have been selected among the articles that have been introduced in the two articles. Classification criteria are as follows: 1) "be learned," "competence," or "be able to function in society" as meanings of "literate," 2) "terms" or "description" as the ways of representing scientific literacy, 3) "singular structure," "hierarchical structure," or "parallel structure" as the inner structure of scientific literacy definitions. The results of this study are as follows: First, hierarchical structures in scientific literacy have almost always accompanied "terms" representing scientific literacy and also accepted the hierarchy between "be learned" and "competence," but not the definition of scientific literacy as functioning in society. All parallel structures in scientific literacy have accompanied the definition as functioning in society. And singular structure almost always appears in researches based on the views of scientific literacy in relatively recent times. Second, researches who have used "terms" as ways of representing scientific literacy have increased. Based on the results in this study, the meanings of scientific literacy have been emphasized in view of the ability of playing a role in a social context as well as learning and competence these days. To meet this movement in scientific literacy actively, science education community should get out of traditional teaching and learning scientific concepts and give emphasis on application in various context and social role of science learners.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.2
• /
• pp.14-25
• /
• 1999

The IEEE standard 1149.1, which was proposed to increase the observability and the controllability in I/O pins, makes it possible the board level testing. In the boundary-scan environments, many shift operations are required due to their serial nature. This increases the test application time and the test application costs. To reduce the test application time, the method based on the parallel opereational multiple scan paths was proposed, but this requires the additional I/O pins and the internal wires. Moreover, it is difficult to make the designs in conformity to the IEEE standard 1149.1 since the standard does not support the parallel operation of data shifts on the scan paths. In this paper, the multiple scan path access algorithm which controls two scan paths simultaneously with one test bus is proposed. Based on the new algorithm, the new algorithm, the new board level BIST architecture which has a relatively small area overhead is developed. The new BIST architecture can reduce the test application time since it can shift the test patterns and the test responses of two scan paths at a time. In addition, it can reduce the costs for the test pattern generation and the test response analysis.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.3
• /
• pp.59-67
• /
• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.10 no.4
• /
• pp.81-93
• /
• 2000

In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.8
• /
• pp.35-45
• /
• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.12
• /
• pp.56-62
• /
• 2013

We present a rectifier for wireless power transmission using multiplier configuration in layout for MOSFETs which works at 13.56 MHz, designed to fit in CMOS process where conventionally used diodes are replaced with the cross-coupled MOSFETs. Full bridge rectifier structure without comparators is employed to reduce current consumption and to be working up to higher frequency. Multiplier configuration designed in layout reduces time delay originated from parasitic series resistance and shunt capacitance at each finger due to long connecting layout, leading to fast transition from on-state to off-state cross-coupled circuit structure and vice versa. The power conversion efficiency is significantly increased due to this fast transition time. The rectifier is fabricated in $0.11{\mu}m$ CMOS process, RF to DC power conversion efficiency is measured as 86.4% at the peak, and this good efficiency is maintained up to 600 MHz, which is, to our best knowledge, the highest frequency based on cross-coupled configuration.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.3 no.2
• /
• pp.39-45
• /
• 2010

In this paper, an equally spaced $3{\times}2$ microstrip patch array antenna based on the fundamental infinite wavelength supported by the composite right/left-handed (CRLH) transmission line (TL) is proposed. The proposed CRLH TL unit cell consists of an inter-digit capacitor to realize left-handed (LH) series capacitance and non-symmetric shunt meander line with a shorted via to realize LH shunt inductance. At the infinite wavelength frequency of 2.09 GHz a 6-port series power divider consisting of a 19 unit cells shows a maximum magnitude difference of 0.73 dB and a $0.52^{\circ}$ maximum phase difference between output ports. The measured resonant frequency and maximum gain of the fabricated array antenna is 2.09 GHz and 10.98 dBi, respectively.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.5
• /
• pp.10-17
• /
• 1989

A new design method of lossy matching network for the microwave broadband ampilfier is presented by using seattering parameters instead od modeling of transistor. A lossy matching network is represented as the combination of 2 lossless networks between which lossy serial or parallel immittance is inserted without using specific topology, and so many useful matching cireuits can be realized. Also it is shown that linear transforming relation exists between gain and reflection coefficient of the amplifier, and the transforming equation is derived using scattering parameters. With this equation some constant gain circles can be drawn on reflection coefficient plane to get adequate reflection coefficient and gain. And since the relations between amplifier gain/reflection coefficient and the immittance of passive element are bilinear transformations. constant gain or reflection coefficients circles. Illustrative examples are presented to show the usefulness of proposed method.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.15 no.3
• /
• pp.1734-1739
• /
• 2014

In this paper, microstrip low pass filter using transmission line with the modified DCRLH structure is designed and fabricated to be removed a spurious resonant mode, and a deep attenuation in stop band. The low pass filter is composed of shunt open-stub to get a deep attenuation and series short-stub to eliminate the spurious harmonics in stop band. In this way, the spurious harmonics occurring on the higher order frequency are suppressed and the filter performance is improved. Insertion loss and VSWR of the fabricated microstrip low pass filter in the passband from DC to 1.5 GHz is 1.26 dB and 1.65, and attenuation on the stopband from 1.84 GHz to 2.18 GHz is less than -100 dB. And also this filter has a good performance for 20 watt power test.