• The Transactions of the Korea Information Processing Society
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• v.5 no.1
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• pp.40-48
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• 1998

Linear size expanders have been studied in many fields for the practical use, which make it possible to connect large numbers of device chips in both parallel communication systems and parallel computers. One major limitation on the efficiency of parallel computer designs has been the highly cost of parallel communication between processors and memories. Linear order concentrators can be used to construct theoretically optimal interconnection network schemes. Existing explicitly defined constructions are based on expanders, which have large constant factors, thereby rendering them impractical for reasonable sized networks. For these objectives, we use the more detailed matching points in permutation functions, to find out the bigger expansion constant from an equation, $\mid\Gamma_x\mid\geq[1+d(1-\midX\mid/n)]\midX\mid$. This paper presents an improvement of expansion constant on constructing concentrators using expanders, which realizes the reduction of the size in a superconcentrator by a constant factor. As a result, this paper shows an explicit construction of (n, 5, $1-\sqrt{3/2}$) expander. Thus, superconcentrators with 209n edges can be obtained by applying to the expanders of Gabber and Galil's construction.

• Journal of Information Management
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• v.29 no.3
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• pp.1-26
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• 1998

The loop is a fundamental for the parallelism exploiting as it has a large portion of execution time for sequential Java program on the parallel machine. This paper proposes the method of exploiting the implicit parallelism through the analysis of data dependence in the existing Java programming language having a single loop structure. The parallel code generation method through the restructuring compiler and the translation method of Java source program into multithread statement, which is supported in the level of the Java programming language, are also proposed here. The performance test of the program translated into the thread statement is conducted using the trip count of loop and the thread count as parameters. The restructuring compiler makes it possible for users to reduce overhead and exploit parallelism efficiently in the Java programming.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.5
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• pp.457-467
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• 2000

본 논문에서는 분산 메모리 구조를 갖는 병렬 컴퓨터 상에서 방대한 크기를 갖는 볼륨 데이터의 효과적인 가시화를 위한 병렬 광선 투사법을 제안한다. 데이터의 압축을 기반으로 하는 본 기법은 다른 프로세서의 메모리로부터 데이터를 읽기보다는 자신의 지역 메모리에 존재하는 압축된 데이터를 빠르게 복원함으로써 병렬 렌더링 성능을 향상시키는 것을 목표로 한다. 본 기법은 객체-순서와 영상-순서 탐색 알고리즘 모두의 정점을 이용하여 성능을 향상시켰다. 즉, 블록 단위의 최대-최소 팔진트리의 탐색과 각 픽셀의 불투명도 값을 동적으로 유지하는 실시간 사진트리를 응용함으로써 객체-공간과 영상-공간 각각의 응집성을 이용하였다. 본 논문에서 제안하는 압축 기반 병렬 볼륨 렌더링 방법은 렌더링 수행 중 발생하는 프로세서간의 통신을 최소화하도록 구현되었는데, 이러한 특징은 프로세서 사이의 상당히 높은 데이터 통신 비용을 감수하여야 하는 PC 및 워크스테이션의 클러스터와 같은 더욱 실용적인 분산 환경에서 매우 유용하다. 본 논문에서는 Cray T3E 병렬 컴퓨터 상에서 Visible Man 데이터를 이용하여 실험을 수행하였다.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.80-86
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• 2002

This paper presents a fast hardware architecture to implement a 2-D DWT(Discrete Wavelet Transform) computed by lifting scheme framework. The conventional 2-D DWT hardware architecture has problem in internal memory, hardware resource, and latency. The proposed architecture was based on the 4-way partitioned data set. This architecture is configured with a pipelining parallel architecture for 4-way partitioning method. Due to the use of this architecture, total latency was improved by 50%, and memory size was reduced by using lifting scheme.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.2
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• pp.110-118
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• 2008

The regulated peak power tracking (RPPT) systems such as the series structure and the parallel structure are commonly used in the satellite space power system. However, this structure processes the solar array power to the load through two regulators during one orbit cycle, which reduces the energy transfer efficiency. The series-parallel structure for the RPPT system can improve the power conversion efficiency, but an additional regulator increases the cost, size and weight of the system. In this paper, a simplified series-parallel space power system that consists of two regulators is proposed. The proposed system has the similar energy transfer efficiency with the series-parallel structure by adding one switch to the series structure, which reduces the cost, size and the weight. The large signal stability analyses is provided to understand the four main modes of system operation. In order to compare the energy efficiency with a series structure, the simulation is performed. The experimental verifications are performed using a prototype hardware with TMS320F2812 DSP and 200W solar arrays.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.383-386
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• 2009

In this paper, we propose some parallel structures of the word-based nonlinear combine functions in word-based stream cipher, high-speed versions of general (bit-based) nonlinear combine functions. Especially, we propose the high-speed structures of popular three kinds in word-based nonlinear combiners using by PS-WFSR (Parallel-Shifting or Parallel-Structured Word-based FSR): m-parallel word-based nonlinear combiner without memory, m-parallel word-based nonlinear combiner with memories, and m-parallel word-based nonlinear filter function. Finally, we analyze its cryptographic security and performance.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10c
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• pp.7-9
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• 2003

기존의 VOD 서비스는 일반적으로 단일 서버 모델을 사용하여 서비스 되어왔다. 그렇지만 단일 서버 모델의 VOD 서비스는 서버 용량의 확장에 따른 오버헤드가 크며 서버 고장시 VOD 서비스를 실시할 수 없는 문제점이 있다. 따라서 이런 문제점들을 해결하고자 병렬 서버 구조에 기반을 둔 VOD 서비스에 대한 연구가 이루어지고 있다. 기존의 유선 네트워크에서의 병렬 서버 구조에 기반을 둔 스트림 전송에 관한 연구가 일부 진행되어 왔지만 무선 네트워크와 관련해선 그러한 연구가 거의 없으며 있어도 아주 이상적인 경우를 가정하였다. 이동통신의 급속한 발전으로 현재 이동국들은 멀티미디어 서비스를 받을 수 있게 되었으며 앞으로는 이동국들에 제공되는 멀티미디어 서비스 역시 QoS가 보장되어야 한다. 따라서 본 논문에서는 무선 모바일 환경에서 병렬 서버 구조를 사용하여 멀티미디어 스트림을 전송함으로서 기지국외 혼잡 상황에도 이동국에서 QoS를 보장할 수 있는 방법을 제시한다. 시뮬레이션 분석 결과를 보면 기지국의 혼잡 상황에서 병렬 서버 구조에 기반을 두고 멀티미디어 스트림을 전송하게 되면 단일 서버로 멀티미디어 스트림을 전송할 때보다 이동국의 수신 상태가 42% 향상됨을 알 수 있다.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.8
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• pp.565-571
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• 2020

In this paper, precision and efficient nonlinear structural analysis for the aircraft wing-box model is developed. Herein, nonlinear shell element based on the co-rotational (CR) formulation is implemented. Then, parallel computing algorithm, the element-based partitioning technique is developed to accelerate the computational efficiency of the nonlinear structural analysis. Finally, computational performance, i.e., accuracy and efficiency, of the proposed analysis is evaluated by comparing with that of the existing commercial software.

• Journal of the Korea Society of Computer and Information
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• v.12 no.3
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• pp.51-58
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• 2007

The shared-nothing multiprocessor architecture has advantages in scalability, this architecture has been adopted in many multiprocessor database system. But, if the data are not uniformly distributed across the processors, load will be unbalanced. Therefore, the whole system performance will deteriorate. This is the data skew problem, which usually occurs in processing parallel hash join. Balancing the load before performing join will resolve this problem efficiently and the whole system performance can be improved. In this paper, we will present an algorithm using merit of very large memory to reduce disk access overhead in performing load balancing and to efficiently solve the data skew problem. Also, we will present analytical model of our new algorithm and present the result of some performance study we made comparing our algorithm with the other algorithms in handling data skew.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2001.11a
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• pp.293-296
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• 2001

본 논문은 GF(2$^{m}$ )상에서 파워썸 연산을 수행하는데 필요한 새로운 알고리즘과 그에 따른 병렬 입/출력 구조를 제안한다. 새로운 알고리즘은 최상위 비트 우선 구조를 기반으로 하고, 제안된 구조는 기존의 구조에 비해 낮은 하드웨어 복잡도와 적은 지연을 가진다. 이는 역원과 나눗셈 연산을 위한 기본 구조로 사용될 수 있으며 암호 프로세서 칩 디자인의 기본 구조로 이용될 수 있고, 또한 단순성, 규칙성과 병렬성으로 인해 VLSI 구현에 적합하다.