• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.4
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• pp.440-446
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• 2011

In this paper, a X-band 50 W pulsed solid state power amplifier(SSPA) is designed and fabricated for radar systems. The SSPA consists of a driver amplifier, a high power amplifier, and a pulse modulator. The high power stage employes four 25 W GaAs FET to deliver 50 W at X-band. To meet the stringent target specification for the SSPA, we used a new hybrid pulse switching method, which combine the advantage of pulse modulation and bias switching method. The fabricated SSPA shows a power gain of 44.2 dB, an output power of 50 W over a 1.12 GHz bandwidth. Also, pulse droop < 1 dB meet the design goals and a rise/fall time is less than 12.45 ns. Fabricated X-band pulsed SSPA size is compact with overall size of $150{\times}105{\times}30\;mm^3$.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.131-143
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• 2006

The rapid growth of mobile communication technology has provided the expansion of mobile internet services, particularly mobile realtime transaction takes much weight among mobile fields. Current mobile transaction service has serious problems which check its development, such as low bandwidths, hand over, expensive charge system, and low response time. but, There is an increasing demand for various mobile applications to process transactions in a mobile computing fields. In mobile computing environments. A mobile host computing system demands for new concurrency control method to use the bandwidth efficiently, to improve the bottleneck and the response time of transactions. This study suggests about an efficient concurrency control in a mobile computing environment. Concurrency control method in existing method uses two phases locking method. In this method, Many clients can't use the same segment simultaneously, and so useless waiting time increases. The characteristic of this proposed method unlike existing one, Enable the transaction approaching different data in the same segment to minimize the useless waiting time by permitting segments, and therefore improves the coexistence of system. Also, It shows the algorithm of the proposed concurrence control method.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.5
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• pp.37-43
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• 2010

When lightning surges with wide frequency spectrum and power converting devices are considered, it is desirable to evaluate grounding system performance by grounding impedances. This paper presents the measured results for frequency-dependent grounding impedance for the vertical grounding electrode and counterpoise on a scale of full size. Grounding impedances of vertical grounding electrodes and counterpoises give capacitive or inductive behaviors according to the length of grounding electrodes and soil resistivity. It is inefficient to extend the length of the grounding electrode in order to decrease the ground resistance, and when designing the grounding system, the consideration of the grounding impedance should be desirable. In order to reduce the grounding impedance of counterpoise, the grounding conductors are jointed at the center of counterpoises. It is effective to reduce the grounding impedance by connecting ground rods to counterpoises in parallel.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.217-219
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• 2018

The method on reconfiguring job priority in service queue has been developed to provide seamless service and to enhance operability of Data Service Platform(DSP) in Korean e-Navigation project that performed by Ministry of Oceans and Fisheries(MOF) since 2016. It plays a critical role for providing seamless services of DSP to expect which services ships request to DSP and how much time it costs to make services for responding them to ships in advance. Therefore, as developing a method on reconfiguring jobs in service queue of DSP with a noble algorithm to analyse priority index in parallel, DSP can provide seamless services to ships regardless of data volume and the number of requests that stacked in service queue.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.55-62
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• 2007

Uptime of embedded processors for mobile devices are dependent on battery consumption. Especially the large portion of power consumption is known to be due to cache management in embedded processors. This paper proposes an energy efficient data cache structure for high performance embedded processors. High performance prefetching data cache issues prefetching instructions before issuing demand-fetch instructions based on reference predictions. These prefetching instruction bring reduction on memory delay by improving cache hit ratio, but on the other hand those increase energy consumption in proportion to the number of prefetching instructions. In this paper, we adopt tag history table on prefetching data cache for reducing energy consumption by minimizing parallel tag comparison. Experimental results show the proposed data cache improves performance on energy consumption as well as memory delay.

• The KIPS Transactions:PartA
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• v.16A no.4
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• pp.223-226
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• 2009

The twisted cube has received great attention as an interconnection network of parallel systems because it has several superior properties, especially in diameter, to the hypercube. It was recently known that, for even m, a mesh of size $2{\times}2^m$ can be embedded into a twisted cube with dilation 1 and expansion 1 and a mesh of size $4{\times}2^m$ with dilation 1 and expansion 2 [Lai and Tsai, 2008]. However, as we know, it has been a conjecture that a mesh with more than eight rows and columns can be embedded into a twisted cube with dilation 1. In this paper, we show that a mesh of size $2^n{\times}2^m$ can be embedded into a twisted cube with dilation 1 and expansion $2^{n-1}$ for even m and with dilation 1 and expansion $2^n$ for odd m where $1{\leq}n{\leq}m$.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.10
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• pp.413-420
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• 2013

Redundant arrays of independent disks (RAID) without a power-fail-safe component in small and mid-sized business suffers from intolerably long resynchronization time after a unclean power-failure. Data blocks and a parity block in a stripe must be updated in a consistent manner, however a data block may be updated but the corresponding parity block may not be updated when a power goes off. Such a partially modified stripe must be updated with a correct parity block. However, it is difficult to find which stripe is partially updated (inconsistent). The widely-used traditional parity resynchronization manner is a intolerably long process that scans the entire volume to find and fix inconsistent stripes. This paper presents a fast resynchronization scheme with a negligible overhead for small and mid-sized RAIDs. The proposed scheme is integrated into a software RAID driver in a Linux system. According to the performance evaluation, the proposed scheme shortens the resynchronization process from 200 minutes to 5 seconds with 2% overhead for normal I/Os.

• Journal of Digital Contents Society
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• v.14 no.2
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• pp.191-197
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• 2013

To complete the "anywhere" mobile service there should not be shaded areas. However, it is never economical to deploy BS's (Base Stations) in a low population density area due to the low resource utilization. We propose a design technique to install RS's(Relay Stations) which are cheaper than BS's and find the condition in which the proposed technique is acceptible. The proposed design technique aims to allocate the frequency and time resources to RS's to minimize the transmission rate degradation due to interferences between RS's as well as to maximize the parallelism in transmission. We showed by simulation that the proposed technique achieves cost benefits when the expected traffic is less than 20.32 percent of the total BS capacity. The proposed technique is compatible with the IEEE 802.16j, thus can be extended to multi-hop configuration.

• Journal of Digital Convergence
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• v.11 no.11
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• pp.421-427
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• 2013

Disk Cache Manager(DCM), a functional server of microkernel based, to improve the I/O power of shared disks is designed and implemented in this work. DCM interfaces other different servers with message passing through ports by serving as a system actor the multi-thread mode on the Minix3 micro-kernel. DCM proposed in this paper uses the shared disk logically as a Seven Disk and Sodd Disk to enable parallel I/O. DCM enables the efficient placement of disk data because it raises disk cache hit-ratio by increasing the cache size when the utilization of the particular disk is high. Through experimental results, we show that DCM is quite efficient for a shared disk with higher utilization.