• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.6
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• pp.127-132
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• 2018

In this paper, a high conversion gain cascode mixer was designed in W-band and verified by the fabrication and measurements. In the high frequency band such as a W-band, the conversion loss of a mixer is increased because of the poor performance of transistors. This high conversion loss of the mixer requires additional circuits which can give an extra gain such as an RF buffer amplifier, and this can affects the linearity and stability of the overall systems. Therefore, it is necessary to maximize the conversion gain of the mixer. To maximize the conversion gain of the mixer, biases of the transistor were optimized, and output load impedance was optimized by the load-pull simulations. The designed mixer was fabricated in $0.1-{\mu}m$ GaAs pHEMT technology and verified by the measurements. The measurement results shows a maximum conversion gain of -4.7 dB at W-band and an input 1-dB compression point of 2.5 dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.9
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• pp.825-833
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• 2016

This paper introduces a direct-conversion CMOS RF transmitter for the IEEE 802.15.4 standard with a low-power high-gain up-conversion mixer designed in $0.18{\mu}m$ process. The designed RF DCT(Direct Conversion Transmitter) is composed of differential DAC(Digital to Analog Converter), passive low-pass filter, quadrature active mixer and drive amplifier. The most important characteristic in designing RF DCT is to satisfy the 2.4 GHz Zigbee standard in low power. The quadrature active mixer inside the proposed RF DCT provides enough high gain as well as sufficient linearity using a gain boosting technique. The measurement results for the proposed transmitter show very low power consumption of 7.8 mA, output power more than 0 dBm and ACPR (Adjacent Channel Power Ratio) of -30 dBc.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.835-840
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• 1993

In this paper a FET mixer is designed realized by small-signal S-parameter using microwave CAD, LINMIC + at Ku-band. The mixer has conversion gain 9.88dB at 14GHz RF, 1GHz IF, and + 1dBm LO imput. The maximum conversion gain is obtained 11.71dB at 1.1GHz. The result shows that the FET mixer does not need pre-and/or IF amplifier. The mixer maintains the desired conversion gain with low LO power level. The conversion gain of the mixer is higher than the available gain of a amplifier, which is experimentally verified.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.522-529
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• 2002

MMIC circuits in whole receiver system was fabricated based on GaAs pHEMT technology. And a V-band downconverter module was fabricated by integrating these circuits. The downconverter module consists of a LO drive power amplifier which generates 24dBm output power, a low noise amplifier(LNA) which shows 20 dB small signal gain, an active parallel feedback oscillator which generates 1.6 dBm output power, and a cascode mixer which shows over 6dB conversion gain. The good conversion gain performance of our mixer made no need to attach any IF amplifier which grows conversion gain. Measured results of the complete downconverter show a conversion gain of over 20 dB between 57.5 GHz and 61.7GHz without IF amplifier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.10
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• pp.1104-1111
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• 2003

The paper presents an algorithm for the compensation of gain and phase imbalances to exist between I-phase and Q-phase signal at direct conversion receiver. We propose a gain and phase imbalances blind equalization compensation algorithm by using variable step-size adaptive loop at direct conversion receiver. The blind equalization schemes have trade-off between convergence speed and jitter effect for the compensation of gain and phase imbalance. We propose the variable step-size adaptive loop method, which varies the loop coefficients according to errors, for recovering these problem. By using variable step-size adaptive loops, we propose to speed up the convergence process and reduce the jitter effect and simulation results show that the algorithm compensates signal loss and speeds up convergence time.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.101-104
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• 2001

In this paper, we propose the Digital Automatic Gain Controller for IEEE 802.11a High-speed Physical Layer in the 5 GHz Band. The input gain is estimated by calculating the energy of the training symbol that is a synchronizing signal. The renewal gain is calculated by comparing the estimated gain with the ideal gain. The renewal gain is converted into the controlled voltage for GCA to reduce or amplify the input signals. We used a piecewise-linear approximation to reduce the hardware size. The gain control is performed seven times to provide more accurate gain control. The proposed automatic gain controller is designed with VHDL and verified by using the Xilinx FPGA.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1508-1509
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• 2007

본 논문에서는 TSMC 0.18um공정을 이용한 무선통신 수신기용 직접변환 방식의 Double Balanced Mixer를 설계 하였다. 제안된 mixer는 current bleeding기법과 내부에 인덕터를 추가하여 기존의 Gilbert Cell구조의 mixer에 비해 변환 이득과 Flicker Noise특성을 향상 시켰다. 모의실험결과 2.45GHz에서 11dB의 변환이득을 나타내었으며 Flicker Noise의 corner frequency는 510kHz이고 이때 잡음특성은 10.8dB이다. 이 회로의 동작전압은 1.8V이며 소모 전력은 8.8mW이다.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1990_1991
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• 2009

본 논문은 뇌파와 같이 측정을 위해서 많은 수의 채널이 필요한 계측 장치에서 채널에 따른 증폭률의 차이를 보정하기 위해 동일한 입력을 가한 후 측정된 시간 영역의 신호를 주파수 영역으로 변환하고 주파수 영역에서의 신호를 분석하여 각 채널의 증폭률의 차이를 유도하고 유도된 증폭률의 차이를 보정하는 알고리즘을 소개한다. 본 논문은 다채널 시스템에서 측정된 신호를 주파수 스펙트럼으로 변환하는 단계와 스펙트럼에서 각 채널의 이득률을 분석하는 단계를 포함하는 다채널 시스템에서 채널간 이득률을 보정하는 방법을 제안한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.780-781
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• 2014

본 논문에서는 차량 추돌 방지 단거리 레이더용 고 변환이득 및 저전력 24GHz CMOS 믹서를 제안한다. 이러한 회로는 2볼트 전원전압에서 동작하며, 저 전압 전원 공급에서도 높은 변환 이득과 낮은 잡음지수를 가지도록 설계되어 있다. 제안한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정($f_T/f_{MAX}=120/140GHz$)으로 설계하였다. 전체 칩 면적을 줄이기 위해 실제 수동형 인덕터 대신 전송선을 이용하였다. 제안한 회로는 최근 발표된 연구결과에 비해 가장 높은 10.96dB의 변환이득, 7.6dBm의 IIP3를 보였고, 가장 적은 5mW의 소비전력 및 $0.2{\times}0.2m^2$의 칩 크기 특성을 보였다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.9
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• pp.31-38
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• 2009

In this paper, we propose new gain optimization method for Sigma-Delta A/D converters. First, in proposed method, the 10 candidates are selected through SNR maximization for Sigma-Delta modulator. After then, it is shown that optimum gains can be obtained through MSE calculation for CIC decimation filter. In the simulation, The proposed method has advantages which utilize SNR maximization for modulator and MSE minimization for CIC decimation later. The more candidates are chosen in SNR maximization for modulator, the better gains can be obtained in MSE minimization for CIC decimation filter.