• Proceedings of the Earthquake Engineering Society of Korea Conference
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• 2002.03a
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• pp.443-450
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• 2002

본 논문에서는 미국토목학회(ASCE)의 사장교에 대한 첫번째 벤치마크 문제를 이용하여 제어-구조물 상호작용을 고려한 새로운 반능동 제어 기법을 제안하였다. 이 벤치마크 문제에서는 2003년 완공 예정으로 미국 Missouri 주에 건설 중인 Cape Girardeau 교를 대상 구조물로 고려하였다. Cape Girardeau 교는 New Madrid 지진구역에 위치하고, Mississippi 강을 횡단하는 주요 교량이라는 점 때문에 설계단계에서부터 내진 문제에 대하여 자세하게 고려되었다. 상세 설계 도면을 기반으로 하여 교량의 전체적인 거동 특성을 정확하게 나타낼 수 있는 3차원 모델이 만들어졌고, 사장교의 제어 성능에 관련된 평가 기준이 수립되었다. 본 연구에서는 제어 가능한 유체 감쇠기에 속하는 MR 유체 감쇠기를 제어 장치로 제안하였고, 기존 연구에서 MR 유체 감쇠기를 포함한 구조물의 제어에 효율적이라고 검증된 clipped-optimal 알고리듬을 제어 알고리듬으로 사용하였다. 또한, 실제 규모의 MR 유체 감쇠기 실험 결과를 이용하여 수치해석에 이용할 수 있는 동적 모델을 개발하였다. MR 유체 감쇠기는 제어 가능한 에너지 소산장치이며 구조물에 에너지를 가하지 않기 때문에 제안된 제어 기법은 한정입출력 안정성이 보장된다. 수치해석을 통해, MR 유체 감쇠기를 이용한 반능동 제어 기법이 사장교의 응답 감소에 효과적인 방법임을 증명하였다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.6
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• pp.259-265
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• 2014

When the trace-driven simulation is used for the performance analysis of widely used multicore processors in the initial design stage, much time and disk space is necessary. In this paper, statistical simulations are performed for a high performance multicore processor with various hardware configurations. For the experiment, SPEC2000 benchmarks programs are used for profiling and synthesizing new instruction traces. As a result, the performance obtained by our statistical simulation is comparable to that of the trace-driven simulation with the benefit of tremendous reduction in the simulation time.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.11
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• pp.836-852
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• 2006

This paper proposes an L1 cache prefetch scheme using an excessively aggressive hardware prefetcher and a hardware prefetch filter having a small direct-mapped filtering cache. A quantitative analysis method has been introduced and applied to analyze nonideal effects of aggressive cache prefetching. From those analysis results, the structure and algorithm of a prefetch filter has been derived and simulated, and the overall system performance has been measured using a cycle-by-cycle cache simulator. Experimental results show that the proposed scheme improves the overall system performance by 18% on the average over several benchmarks

• Journal of the Korea Computer Industry Society
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• v.6 no.3
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• pp.559-566
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• 2005

ALTIBASE is the relational main memory DBMS that enables us to develop the high performance and fault tolerant applications. It guarantees the short and predictable execution time as well as the basic functionality of conventional disk-based DBMS. We present the overview of system architecture and the performance analysis with respect to the various design choices. The assorted experiments are performed under the various environments. The results of TPC-H and Wisconsin benchmark tests are described. We illustrate the various performance comparisons under the various index mechanisms, the replication models, the transaction durabilities, and the application structures. A performance study shows the ALTIBASE system can be applied to the wide area of industrial DBMS fields.

• The Journal of the Korea Contents Association
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• v.15 no.4
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• pp.9-16
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• 2015

On modern operating systems such as Linux, virtual memory is a general way to provide a large address space to applications by using main memory and storage devices. Recently, storage devices have been improved in terms of latency and bandwidth, and it is expected that applications with large memory show high-performance if next-generation storage devices are considered. However, due to the overhead of virtual memory subsystem, the paging system can not exploit the performance of next-generation storage devices. In this study, we propose several optimization techniques to extend memory with next-generation storage devices. The techniques are to allocate block addresses of storage devices for write-back operations as well as to configure the system parameters, and we implement the techniques on Linux 3.14.3. Our evaluation through using multiple benchmarks shows that our system has 3 times (/24%) better performance on average than the baseline system in the micro(/macro)-benchmark.

• The KIPS Transactions:PartA
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• v.10A no.2
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• pp.123-130
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• 2003

This paper presents a new striped checkpointing scheme for serverless cluster computers, where the local disks are attached to the cluster nodes collectively form a distributed RAID with a single I/O space. Striping enables parallel I/O on the distributed disks and staggering avoids network bottleneck in the distributed RAID. We demonstrate how to reduce the checkpointing overhead and increase the availability by striping and staggering dynamically for communication intensive applications. Linpack HPC Benchamark and MPI programs are applied to these checkpointing schemes for performance evaluation on the 16-nodes cluster system. Benchmark results prove the benefits of the striped checkpointing scheme compare to the existing schemes, and these results are useful to design the efficient checkpointing scheme for fast rollback recovery from any single node failure in a cluster system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.157-163
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• 2016

If trace-driven or execution-driven simulation is used for the performance analysis of asymmetric multi-core processors, excessive time and much disk space are necessary. In this paper, statistical simulations are performed for asymmetric multi-core processors with various hardware configurations. For the experiment, SPEC 2000 benchmark programs are used for profiling and synthesis, which is supplied as input for the simulation of asymmetric multi-core processors. As a result, the performance of asymmetric multi-core processor obtained by statistical simulation is comparable to that of the trace-driven simulation with a tremendous reduction in the simulation time.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.5
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• pp.297-305
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• 2006

Trace-driven simulation is widely used for measuring the performance of a microprocessor in its initial design phase. However, since it requires much time and disk space, the statistical simulation has been studied as an alternative method. In this paper, statistical simulations are performed for a high performance superscalar microprocessor with a perceptron-based multiple branch predictor. For the verification, various hardware configurations are simulated using SPEC2000 benchmarks programs as input. As a result, we show that the statistical simulation is quite accurate and time saving for the evaluation of microprocessor architectures with multiple branch prediction.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.4
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• pp.204-212
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• 2001

본 논문에서는 조합논리회로의 테스트 컴팩션을 위한 두 가지 효율적인 알고리즘을 제안한다. 제안된 알고리즘들은 각각 동적인 컴팩션 기법과 정적인 컴팩션 기법을 사용하고 있으며, 실험을 위해 기존의 ATPG시스템인 ATALANTA에 통합 구현하였다. ISCAS85와 ISCAS89(완전스캔 버전) 벤치마크 회로에 대한 실험에서 본 시스템은 기존에 발표된 다른 컴팩션 알고리즘에 비하여 보다 작은 테스트 집합을 보다 빠르게 생성하였으며, 실험 결과를 통하여 제안된 알고리즘들의 유효성을 입증할 수가 있었다.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06b
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• pp.350-352
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• 2011

마이크로 프로세서의 퍼포먼스 카운터는 프로그램의 병목 현상을 분석할 수 있는 중요한 도구이다. 퍼포먼스 카운터를 사용하면 다양한 이벤트의 출현 빈도를 성능의 저하 없이 정확하게 측정할 수 있다는 장점이 있다. 특히 퍼포먼스 카운터는 현재 널리 사용되고 있는 멀티코어 프로세서의 성능을 분석하는데 유효하다. 본 논문에서는 인텔 네할렘 프로세서의 확장된 퍼포먼스 카운터를 이용하여 멀티코어 프로세서의 성능을 분석하는 기법을 소개하고자 한다. 본 논문에서는 네할렘 아키텍쳐를 적용한 인텔 Xeon 시리즈 프로세서와 SPEC CPU 2006벤치마크를 이용하여 성능을 분석한다.