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The Processor Performance Model Using Statistical Simulation  

Lee Jong-Bok (한성대학교 정보통신공학과)
Abstract
Trace-driven simulation is widely used for measuring the performance of a microprocessor in its initial design phase. However, since it requires much time and disk space, the statistical simulation has been studied as an alternative method. In this paper, statistical simulations are performed for a high performance superscalar microprocessor with a perceptron-based multiple branch predictor. For the verification, various hardware configurations are simulated using SPEC2000 benchmarks programs as input. As a result, we show that the statistical simulation is quite accurate and time saving for the evaluation of microprocessor architectures with multiple branch prediction.
Keywords
statistical simulation; superscalar processor; multiple branch prediction;
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1 D. A. Jimenez and C. Lin, 'Dynamic Branch Prediction with Perceptrons,' in Proceedings of the Seventh International Symposium on High Performance Computer Architecture, 2001. pp. 197-206   DOI
2 D. A. Jimenez and C. Lin, 'Neural Methods for Dynamic Branch Prediction,' ACM Transactions on Computer Systems, vol. 20, pp. 369-397, 2002   DOI   ScienceOn
3 T-Y. Yeh and Y. N. Patt, 'Two-Level Adaptive Branch Prediction,' in The 24th ACM/IEEE International Symposium and Workshop on Microarchitectures, Nov. 1991, pp. 51-61
4 The SPARC Architecture Manual, Prentice-Hall, Inc., 1992
5 Introduction to Shade, Sun Microsystems, Inc., Jun. 1997
6 T-Y. Yeh, D. T. Marr, and Y. N. Patt, 'Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache,' in The 7th International Conference on Supercomputing, Jul. 1993, pp, 67-76   DOI
7 R. Rakvic, B. Black, and J. P. Shen, 'Completion Time Multiple Branch Prediction for Enhancing Trace Cache Performance,' in Annual International Symposium on Computer Architecture, 2000, pp. 47-58   DOI
8 S. Nussbaum and J. E. Smith, 'Modeling Super-scalar Processors via Statistical Simulation,' in International Conference on Parallel Architectures and Compilation Techniques, Sep. 2001, pp. 15-24
9 E. Rotenberg, S. Benett, and J. E. Smith, 'Trace Cache : a Low Latency Approach to High Bandwidth Instruction Fetching,' in Proceedings of the 29th Annual International Symposium on Microarchitecture, Dec. 1996, pp, 24-34
10 L. Eeckout, R. H. Bell Jr., B. Stougie, K. D. Bosschere, and L. K. John, 'Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies,' in International Symposium on Performance Analysis of Systems and Software, 2004   DOI