• Transactions of the Korean Society of Automotive Engineers
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• v.18 no.6
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• pp.14-22
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• 2010

In this study, a large bus is tested for measuring the steering response based on the slarom test and step steer test. A full car model by using ADAMS/Car is established for computer simulation. For bus modeling, user defined templates are made and used in the simulation. Simulation results according to the slarom and step steer test are compared to the physical experiments, in which several sensors are installed to measure vehicle responses. The results obtained from the comparison show a good agreement with regard to the vehicle velocity and steering angle.

• Journal of the Korea Society of Computer and Information
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• v.24 no.11
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• pp.1-9
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• 2019

In this paper, we propose a Small Active Command scheme which reduces the power consumption of the command bus to DRAM. To do this, we target the ACTIVE command, which consists of multiple packets, containing the row address that occupies the largest size among the addresses delivered to the DRAM. The proposed scheme identifies frequently referenced row addresses as Hot pages first, and delivers index numbers of small caches (tables) located in the memory controller and DRAM. I-ACTIVE and I-PRECHARGE commands using unused bits of existing DRAM commands are added for index number transfer and cache synchronization management. Experimental results show that the proposed method reduces the command bus power consumption by 20% and 8.1% on average in the close-page and open-page policies, respectively.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.4
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• pp.188-195
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• 2001

본 논문에서는 PC 클러스터 기반 CC-NUMA 시스템을 제안하고, 시뮬레이션을 통하여 성능을 분석하였다. PC 클러스터 기반 CC-NUMA 시스템은 PC의 PCI slot에 CC-NUMA 카드를 장착함으로써 구현되며 공유메모리, 네트워크 캐쉬, 네트워크 제어 모듈을 포함한다. CC-NUMA 시스템은 PCI 버스상에 존재하는 메모리를 공유대상으로 하며, 공유메모리와 네트워크 캐쉬사이의 일관성은 IEEE SCI 표준에 의해 유지된다. CC-NUMA 시스템을 시뮬레이션 하기 위해 실행주도 시뮬레이터인 Limes를 수정하여 사용하였으며, 캐쉬 일관성 유지 알고리즘으로 SCI의 typical set을 구현하였다. 또한 기존 시스템과의 비교를 위해서 네트워크 캐쉬를 활용하지 않는 Dolphin사의 PCI-SCI 카드에 기반한 NUMA 시스템을 시뮬레이션 하였다. CC-NUMA 시스템의 성능을 측정하기 위하여 다양한 실험을 수행하였으며, 실험결과 CC-NUMA 시스템이 NUMA 시스템에 비해서 성능향상이 우수함을 알 수 있었다. 또한, CC-NUMA 시스템이 최적의 성능을 발휘하는 파라미터의 값을 도출하였으며, 이를 CC-NUMA 시스템의 실제 구현에 반영하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.65-72
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• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.5
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• pp.14-22
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• 2011

This study is to estimate delay time model of signalized intersection by using travel data of Bus Information System. BIS, which applies the advanced information technology to an existing bus system, has been developing and operating in many cities. However, even though some useful traffic informations have been collected from BIS operation, utilization of real-time data to the traffic operation has not been promoted due to the inhomogeneity of modal speeds. Accordingly, in this study, a fundamental research is performed for traffic controls in urban areas and providing a traffic information throughout a methodology for estimating delay time using the data from BIS was developed. This delay time model setting bus travel time excluding service time of a bus stop as explanatory variables was constructed as a regression model, and the coefficient of determination of a linear regression model most highly appeared as 0.826. As a result of performing T-test with field survey values and model estimation values for verifying constructed models statistically, it was analyzed to be statistically significant in a confidence level of 95%.

• Journal of KIISE:Information Networking
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• v.30 no.4
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• pp.494-503
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• 2003

The IEEE 1394 High Speed Serial Bus is a versatile, high-performance, and low-cost method of promoting interoperability between all types of A/V and computing devices. IEEE 1394 provides two transfer modes: asynchronous mode for best effort service and isochronous mode for best effort service with bandwidth reservation. This paper shows the bus performance and compared the transfer odes first at the link level and then at the application level. For the application level performance, we analyze the bus systems with fixed and adaptive interfaces, applied between the upper layer and the 1394 layer, using polling systems. Also we verifies the analysis models with simulation studies. Based on our analysis, we conclude that the adaptive interface reduces the bus access time and so increases the bus utilization.

• Journal of IKEEE
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• v.28 no.1
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• pp.116-122
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• 2024

AMBA AHB-Lite bus is widely used in on-chip bus protocol for low-power and cost-effective SoC. However, it lacks built-in error detection and correction for end-to-end data integrity. This can lead to data corruption and system instability, particularly in harsh environments like automotive applications. To mitigate this problem, this paper proposes the application of SEC-DED (Single Error Correction-Double Error Detection) to AMBA AHB-Lite bus. It aims not only to detect errors in real-time but also to correct them, thereby enhancing end-to-end data integrity. Simulation results demonstrate real-time error detection and correction when errors occur, which bolsters end-to-end data integrity of automotive on-chip bus.

• The KIPS Transactions:PartD
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• v.14D no.6
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• pp.649-656
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• 2007

Today, controller area network(CAN) is a field bus that is nowadays widespread in distributed embedded systems due to its electrical robustness, low price, and deterministic access delay. However, its use safety-critical applications has been controversial due to dependability limitation, such as those arising from its bus topology. Thus it is important to analyze the performance of the network in terms of load of data bus, maximum time delay, communication contention, and others during the design phase of the controller area network. In this paper, a simulation algorithm is introduced to evaluate the communication performance of the vehicle network and apply software base fault injection techniques. This can not only reduce any erratic implementation of the vehicle network but it also improves the reliability of the system.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.133-140
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• 2002

Distributed-queue Dual-Bus (DQDB) shows an unfair behavior in bandwidth allocation due to the nature of unidirectional bus architecture. The study on fairness control method for DQDB has been performed under specific load types such as equal Probability load. symmetric load and asymmetric load type. A client-server load type is more practical traffic pattern than specific load type in Web environments. In this paper, we propose an effective fairness control method to distribute DQDB network bandwidth fairly to all stations under Web environments. The proposed method directly calculates an access limit from the bandwidth demand pattern. Based on an access limit, it controls the allocation of bandwidth by yielding empty slots in clients to servers. And we were certain that it outperforms other mechanisms from simulation results.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.2
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• pp.38-44
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• 2003

In this paper, we propose the method in which multimedia data simultaneously transfers to the main memory and the multimedia processor from the network interface card to improve bottleneck of system bus through analysis for architecture of video conference system and input/output model. The proposed method can reduce the number of system bus accesses, bus cycles, data transmission time and compression ratio of video data in the video conference system. We compared the performance between the proposed method and the conventional methods in the multi-party video conference systems. The simulation results showed that the proposed method was reduced the transmission time of multimedia data than the conventional method.