Browse > Article
http://dx.doi.org/10.9708/jksci.2019.24.11.001

Small Active Command Design for High Density DRAMs  

Lee, Kwangho (Dept. of Computer Engineering, Won-Kwang University)
Lee, Jongmin (Dept. of Computer Engineering, Won-Kwang University)
Abstract
In this paper, we propose a Small Active Command scheme which reduces the power consumption of the command bus to DRAM. To do this, we target the ACTIVE command, which consists of multiple packets, containing the row address that occupies the largest size among the addresses delivered to the DRAM. The proposed scheme identifies frequently referenced row addresses as Hot pages first, and delivers index numbers of small caches (tables) located in the memory controller and DRAM. I-ACTIVE and I-PRECHARGE commands using unused bits of existing DRAM commands are added for index number transfer and cache synchronization management. Experimental results show that the proposed method reduces the command bus power consumption by 20% and 8.1% on average in the close-page and open-page policies, respectively.
Keywords
DRAMs; Low-power; Index-based Activation; Memories; Simulation;
Citations & Related Records
연도 인용수 순위
  • Reference
1 JEDEC Solid State Technology Association, Lower Double Data Rate 4 (LPDDR4), August 2014, https://www.jedec.org
2 JEDEC Solid State Technology Association, High Bandwidth Memory (HBM), October 2013, https://www.jedec.org
3 K. Lim, P. Ranganathan, J. Chang, C. Patel, T. Mudge, and S. Reinhardt, "Understanding and designing new server architectures for emerging warehouse-computing environments," Proceedings of the 35th Annual International Symposium on Computer Architecture (ISCA), pp. 315-326, Beijing, China, 2008.
4 D. Meisner, B. T. Gold, and T. F. Wenisch, "PowerNap: Eliminating server idle power," Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XIV), pp. 205-216, Washington DC, USA, 2009.
5 H. Zheng, J. Lin, Z. Zhang, E. Gorbatov, H. David, and Z. Zhu, "Mini-rank: Adaptive DRAM Architecture for Improving Memory Power Efficiency," Proceedings of the 41st IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 210-221, Lake Como, Italy, 2008.
6 Y. Lee, S. Kim, S. Hong, and J. Lee, "Skinflint DRAM System: Minimizing DRAM Chip Writes for Low Power," Proceedings of the 19th International Symposium on High Performance Computer Architecture (HPCA), pp. 25-34, Shenzhen, China, 2013.
7 J. Ahn, N. P. Jouppi, C. Kozyrakis, J. Leverich, and R. S. Schreiber, "Future Scaling of Processor-memory Interfaces," Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis (SC), pp. 1-12, Portland, USA, 2009.
8 A. N. Udipi, N. Muralimanohar, N. Chatterjee, R. Balasubramonian, A. Davis, and N. P. Jouppi, "Rethinking DRAM Design and Organization for Energy-constrained Multi-cores," Proceedings of the 37th annual International Symposium on Computer Architecture (ISCA), pp. 175-186, Saint-Malo, France, 2010.
9 D. Shin, S. Park, S. Kim, and K. Park, "Adaptive Page Grouping for Energy Efficiency in Hybrid PRAM-DRAM Main Memory," Proceedings of the 2012 ACM Research in Applied Computation Symposium, pp. 395-402, San Antonio, USA, 2012.
10 Thaleia Dimitra Doudali, Sergey Blagodurov, Abhinav Vishnu, Sudhanva Gurumurthi, and Ada Gavrilovska, "Kleio: A Hybrid Memory Page Scheduler with Machine Intelligence." In Proceedings of the 28th International Symposium on High-Performance Parallel and Distributed Computing (HPDC), pp. 37-48, New York, USA, 2019
11 N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, "CACTI 6.0: A Tool to Model Large Caches," HP Laboratories, 2009.
12 L. Ramos, E. Gorbatov, and R. Bianchini, "Page Placement in Hybrid Memory Systems," Proceedings of the International Conference on Supercomputing (ICS), pp. 85-95, Tucson, USA, 2011.
13 I. Shin, "Hot/cold clustering for page mapping in NAND flash memory," in IEEE Transactions on Consumer Electronics, Vol. 57, No. 4, pp. 1728-1731, November 2011. DOI:10.1109/TCE.2011.6131147   DOI
14 B. Jacob, S. W. Ng, and D. Wang, "Memory Systems: Cache, DRAM, Disk," Morgan Kaufmann Publishers, 2007.
15 Z. Zhang, Z. Zhu, and X. Zhang, "A Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality," Proceedings of the 33rd IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 32-41, Monterey, USA, 2000.
16 N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood, "The Gem5 Simulator," SIGARCH Computer Architecture News, Vol. 39, No 2, May 2011.
17 J. L. Henning, "SPEC CPU2006 Benchmark Descriptions," ACM SIGARCH Computer Architecture News, pp. 1-17, September 2006. https://www.spec.org
18 K. Ning and D. Kaeli, "Bus Power Estimation and Power-Efficient Bus Arbitration for System-on-a-Chip Embedded Systems," Proceedings of the 4th International Conference on Power-Aware Computer Systems (PACS), pp. 95-106, Portland, USA, 2004.
19 D. Liu and C. Svensson, "Power Consumption Estimation in CMOS VLSI Chips," IEEE Journal of Solid-State Circuits, Vol. 29, Issue 6, pp. 663-670, 1994. DOI:10.1109/4.293111   DOI