• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.5
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• pp.1-7
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• 2008

The general bus architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. Specially, as several masters do not concurrently receive the right of bus usage, the arbiter plays an important role in arbitrating between shared bus and masters. Fixed priority, round-robin, TDMA and Lottery methods are developed in general arbitration policies, which lead the efficiency of bus usage in shared bus. On the other hand, the bus architecture can be modified to maximize the system performance. In the paper, we propose the flying master bus architecture that supports the parallel bus communication and analyze its merits and demerits following various arbitration policies that are mentioned above, compared with normal shared bus. From the results of performance verification using TLM(Transaction Level Model), we find that more than 40% of the data communication performance improves, regardless of arbitration policies. As the flying master bus architecture advances its studies and applies various SoCs, it becomes the leading candidate of the high performance bus architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.26-32
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• 2008

The conventional shared bus architecture is capable of processing only one data transaction in same time. In this paper, we propose the NAWM (No Arbitration Wild Master) bus architecture that is capable of processing several data transactions in same time. After designing the master and the slave wrappers of NAWM bus architecture about AMBA system, we confirm that most of IPs of AMBA system can be a lied without modification and the added timing delay can be neglected. from simulation we deduce that more than 50% parallel processing is possible when several masters initiate slaves in NAWM bus architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2261-2266
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• 2012

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance analysis of Fixed Priority, Round Robin, TDMA and Lottery bus arbitration policies due to the data traffic concentration and propose the methods of performance improvement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.54-60
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• 2008

The bus architecture consists of a master initiating a communication transaction, a slave responding to the transaction, a arbiter selecting a master, a bridge connecting buses and so on. Recently this is more complicated and developed toward multi-bus architecture. In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory selector is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

• Review of KIISC
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• v.32 no.4
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• pp.19-32
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• 2022

메타버스는 인공지능, 블록체인, 네트워크, 가상 현실, 착용 가능한 기기 등 수많은 현대 기술들이 발전하면서 서로 융합되어 생성된 대규모 디지털 가상화 세계이다. 현재 메타버스 기반 다양한 플랫폼들이 대중화되면서 산업계 및 연구계에서는 메타버스의 발전에 주목하고 있으며, 긍정적인 시장 전망을 예상하고 있다. 하지만, 아직까지 메타버스 세계에서 발생할 수 있는 보안 위협 요소 및 대책에 관한 연구는 상대적으로 부족하다. 메타버스는 새로운 패러다임의 컨텐츠 및 서비스를 제공하고, 기존 IT 환경에서보다 방대하고 예민할 수 있는 사용자의 데이터를 요구하며, 여러 IT 기술들이 결합된 시스템인 만큼 고려해야 할 보안 위협 요소들이 많다. 본 논문에서는 메타버스 아키텍처를 소개하고, 사용자의 이용 환경, 가상 환경 및 디지털 트윈 환경에서 발생할 수 있는 보안 위협 요소들에 대해 제시하면서, 이에 대해 메타버스 서비스 제공자, 사용자 및 관련 제도 관리자들이 고려할 수 있는 대책들에 대해 소개한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1879-1884
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• 2013

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance analysis of Fixed Priority, Round Robin, TDMA and Lottery bus arbitration policies due to the data traffic concentration and propose the methods of performance improvement.

• Journal of the Korea Society of Computer and Information
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• v.28 no.9
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• pp.63-71
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• 2023

Metaverse is a modern new technology that is advancing quickly. The goal of this study is to investigate this technique from the perspective of computer vision as well as general perspective. A thorough analysis of computer vision related Metaverse topics has been done in this study. Its history, method, architecture, benefits, and drawbacks are all covered. The Metaverse's future and the steps that must be taken to adapt to this technology are described. The concepts of Mixed Reality (MR), Augmented Reality (AR), Extended Reality (XR) and Virtual Reality (VR) are briefly discussed. The role of computer vision and its application, advantages and disadvantages and the future research areas are discussed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.2009-2014
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• 2012

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance comparison of TDMA and Lottery bus arbitration policy developed recently due to farious conditions and propose the methods of performance improvement.

• Electronics and Telecommunications Trends
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• v.38 no.2
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• pp.75-84
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• 2023

Metaverse is expected to bring many innovations to society, culture, and economy by providing realistic services in various fields while suppressing time and space constraints. However, unclear definitions owing to the high diversity of the metaverse add to the confusion of the ecosystem participants. The current metaverse service has many voices of concern owing to technical limitations and lack of a clear profit model. Nevertheless, given its high growth potential driven by the digital transformation, a solid and long-term technology development strategy seems to be necessary. Accordingly, we analyze development cases centering on the major metaverse service shapes presented in the Metaverse New Industry Leading Strategy announced by the Ministry of Science and ICT in January 2022. In addition, we study the characteristics and core technologies of each metaverse service for its realization and discuss future stages of technological development.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.96-102
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• 2008

The SoC bus topology is classified to single and multiple bus systems due to bus number. In single bus system, the selected only one master among the masters that try to initiate the bus transaction can execute its data transaction. On the other hand, in multiple bus system, as several buses that can be operated independently are connected with bridge, multiple data can be transferred parallel in each bus. However, In the case of data communication from one bus system to the other, data latency has remarkably increased in multiple bus. Furthermore, the performance of multiple bus can be easily different from master number, slave type and so on. In this paper, the performance of single and multiple bus architecture is compared and quantitatively analysed with the variation of master number and slave type especially a tying SDRAM, SRAM and register with TLM simulation method.