• Composites Research
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• v.35 no.2
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• pp.69-74
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• 2022

In this study, the conductive paste used in a wide range such as wiring in the electronic packaging field, the automobile industry, and electronic products is manufactured under various process conditions due to the simplicity of the process, and then the thermal, mechanical, and electrical characteristics are analyzed and simulation studies are conducted to optimize the process. to establish the conditions of the conductive paste manufacturing process. First, a conductive paste was prepared by setting various types of binder resin, an essential component of the conductive paste, and characteristics such as thermal conductivity, tensile strength, and elongation were analyzed. Among the binder resins, the conductive paste applied with a flexible epoxy material had the best physical properties, and a simulation study was conducted based on the physical property data base of the conductive face. As a result of the simulation, the best physical properties were exhibited when the Ag flake volume fraction was 60%.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.37-39
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• 2001

반도체 설계는 급속한 기능 추가와 기가 헬쯔에 육박하는 고속 동작에 부응하는 제품의 설계와 빠른 출시를 위하여 다방면의 연구를 거듭하고 있다. 하지만, 인터넷과 정보 가전의 모바일 기기에서 요구하는 폭발적인 기능의 추가와 가전기기의 최소화를 위하여서는 그 요구를 감당하지 못하고 있다. 이를 위한 방안으로 설계 재활용과 System-On-Chip의 설계가 수년 전부터 대두되었으나 아직 큰 실효를 거두지 못하고 있다. SoC설계는 다기능을 한 칩에 구성하는 방법을 시도하고 있고, 설계 재활용은 기존의 설계(IP)를 다른 것과 혼합하여 필요한 기능을 제공하는 방법이 시도되고 있다. 이 두가지의 VLSI 설계 방식 흐름을 가능하도록 하기 위한 연구로써, 레이아웃 이식에 관한 연구를 진행하였다. IP 재활용을 위하여서는 다양한 공정변화에 신속히 대응하고, 기존의 설계 설계규칙으로 설계된 면을 현재의 공정인 0.25um, 0.18um 테크놀러지에 맞도록 변환하는 VLSI 소프트웨어 시스템을 필요로 한다. 레이아웃 설계도면을 분석하여 소자 및 배선을 인식하는 알고리즘을 연구와 개발하고, 도면을 첨단 테크놀러지의 설계 규칙에 부응하도록 타이밍, 소비 전력, 수율을 고려한 최적의 소자 및 배선의 크기를 조절하는 방법을 고안하며, 칩 면적을 최적화할 수 있는 컴팩션 알고리즘을 개발하여 레이아웃 설계 도면을 이식할 수 있는 자동화 소프트웨어 시스템을 연구하였다. 더불어, 현재 반도체 소프트웨어 시스템의 최대 문제점에 해당하는 처리 속도와 도면의 처리 능력을 비교, 검토하여 본 연구가 속도면에서 평균 27배 효율면에서 3배 이상의 상대우위를 점하였다.전송과 복원이 이루어질 것이다.하지 않은 경우 단어 인식률이 43.21%인 반면 표제어간 음운변화 현상을 반영한 1-Best 사전의 경우 48.99%, Multi 사전의 경우 50.19%로 인식률이 5~6%정도 향상되었음을 볼 수 있었고, 수작업에 의한 표준발음사전의 단어 인식률 45.90% 보다도 약 3~4% 좋은 성능을 보였다.으로서 hemicellulose구조가 polyuronic acid의 형태인 것으로 사료된다. 추출획분의 구성단당은 여러 곡물연구의 보고와 유사하게 glucose, arabinose, xylose 함량이 대체로 높게 나타났다. 점미가 수가용성분에서 goucose대비 용출함량이 고르게 나타나는 경향을 보였고 흑미는 알칼리가용분에서 glucose가 상당량(0.68%) 포함되고 있음을 보여주었고 arabinose(0.68%), xylose(0.05%)도 다른 종류에 비해서 다량 함유한 것으로 나타났다. 흑미는 총식이섬유 함량이 높고 pectic substances, hemicellulose, uronic acid 함량이 높아서 콜레스테롤 저하 등의 효과가 기대되며 고섬유식품으로서 조리 특성 연구가 필요한 것으로 사료된다.리하였다. 얻어진 소견(所見)은 다음과 같았다. 1. 모년령(母年齡), 임신회수(姙娠回數), 임신기간(姙娠其間), 출산시체중등(出産時體重等)의 제요인(諸要因)은 주산기사망(周産基死亡)에 대(對)하여 통계적(統計的)으로 유의(有意)한 영향을 미치고 있어 $25{\sim}29$세(歲)의 연령군에서, 2번째 임신과 2번째의 출산에서 그리고 만삭의 임신 기간에, 출산시체중(出産時體重) $

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.69-74
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• 2010

A new package substrate for dynamic random access memory(DRAM) devices has been developed using selective aluminum anodization. Unlike the conventional substrate structure commonly made by laminating epoxy-based core and copper clad, this substrate consists of bottom aluminum, middle anodic aluminum oxide and top copper. Anodization process on the aluminum substrate provides thick aluminum oxide used as a dielectric layer in the package substrate. Placing copper traces on the anodic aluminum oxide layer, the resulting two-layer metal structure is completed in the package substrate. Selective anodization process makes it possible to construct a fully filled via structure. Also, putting vias directly in the bonding pads and the ball pads in the substrate design, via in pad structure is applied in this work. These arrangement of via in pad and two-layer metal structure make routing easier and thus provide more design flexibility. In a substrate design, all signal lines are routed based on the transmission line scheme of finite-width coplanar waveguide or microstrip with a characteristic impedance of about $50{\Omega}$ for better signal transmission. The property and performance of anodic alumina based package substrate such as layer structure, design method, fabrication process and measurement characteristics are investigated in detail.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.8-18
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• 2000

We presented a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. As the frequency of RF system devices increases, the effect of its electrical parasitics in the wireless communication system requires new structure of RF circuit modules because of its needs to be considered of electrical performance for minimization and module mobility. RF circuit modules with BGA packages can provide some advantages such as minimization, shorter circuit routing, and noise improvement by reducing electrical noise affected to analog and digital mixed circuits, etc. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and measured electrical parameters with a TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3${\times}$3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, and self inductance 146pH, whose values were reduced to 34% and 47% of the value of QFP package structure. S11 parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55GHz and the loss of 0.26dB. Routing length of the substrate was reduced to 39.8mm. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.2
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• pp.29-35
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• 2017

In this paper, we investigated a manufacturing process of metal micro-wire interconnection on submillimeter diameter catheter. Over the years, flexible electronic researches have focused on flexible plane polymer substrate and micro electrode manufacturing on its surface. However, a curved polymer substrate, such as catheter, is very important for medical application. Among many catheters, importance of submillimeter diameter steerable catheter is increasing to resolve the several limitations of neurosurgery. Steering actuators have been researched for realizing the steerable catheter, but there is no research about practical wiring for driving these actuators. Therefore we developed a new manufacturing process for metal micro-wire interconnection on submillimeter diameter catheter. We designed custom jigs for alignment of the metal micro-wires on the submillimeter diameter catheter. An UV curing system and commercial products were used to reduce the manufacturing time and cost; Au micro-wire, UV curable epoxy, UV lamp, and submillimeter diameter catheter. The assembled catheter was characterized by using an optical microscope, a resistance meter, and a universal testing machine.

• Journal of the Korean Vacuum Society
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• v.7 no.3
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• pp.267-267
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• 1998

The fluorine doped silicon oxide (SiOF) intermetal dielectric (IMD) films have been of interest due to their lower dielectric constant and compatibility with existing process tools. However instability issues related to bond and increasing dielectric constant to water absorption when the SiOF films was exposured to atmospheric ambient. Therefore, the purpose of this research is to study the effect of post oxygen plasma treatment on the resistance of moisture absorption and reliability of SiOF film. Improvement of moisture absorption resistance of SiOF film is due to the forming of thin SiO₂layer at the SiOF film surface. It is thought that the main effect of the improvement of moisture absorption resistance was densification of the top layer and reduction in the number of Si-F bonds that tend to associate with OH bonds. However, the dielectric constant was increased when plasma treatment time is above 5 min. In this study, therefore, it is thought that the proper plasma treatment time is 3 min when plasma treatment condition is 700 W of microwave power, 3 mTorr of process pressure and 300℃ of substrate temperature.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.3 s.40
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• pp.47-51
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• 2006

Recently, CMP (Chemical Mechanical Polishing) is one of very important processing in semiconductor technology because of large integration and application of design role. CMP is a planarization process of wafer surface using the chemical and mechanical reactions. One of the most important components of the CMP system is the polishing pad. During the CMP process, the pad itself becomes smoother and glazing. Therefore it is necessary to have a pad conditioning process to refresh the pad surface, to remove slurry debris and to supply the fresh slurry on the surface. A conditioning disk is used during the pad conditioning. There are diamonds on the surface of diamond disk to remove slurry debris and to polish pad surface slightly, so density, shape and size of diamond are very important factors. In this study, we characterized diamond disk with 9 kinds of sample.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.111-119
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• 2005

Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

• Korean Chemical Engineering Research
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• v.53 no.4
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• pp.517-523
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• 2015

As the aluminum (Al) metallization process was replaced with copper (Cu), the damascene process was introduced, which required the planarization step to eliminate over-deposited Cu with Chemical Mechanical Polishing (CMP) process. In this study, the verification of the corrosion inhibitors, one of the Cu CMP slurry components, was conducted to find out the tendency regarding the carboxyl and amino functional group in neutral environment. Through the results of etch rate, removal rate, and chemical ability of corrosion inhibitors based on 1H-1,2,4-triazole as the base-corrosion inhibitor, while the amine functional group presents high Cu etching ability, carboxyl functional group shows lower Cu etching ability than base-corrosion inhibitor which means that it increases passivation effect by making strong passivation layer. It implies that the corrosion inhibitor with amine functional group was proper to apply for 1st Cu CMP slurry owing to the high etch rate and with carboxyl functional group was favorable for the 2nd Cu CMP slurry due to the high Cu removal rate/dissolution rate ratio.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.37-43
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• 2008

This paper introduces a high-speed low-power self-timed current-mode logic (STCML) that reduces both dynamic and leakage power dissipation. STCML significantly reduces the leakage portion of the power consumption using a pulse-mode control for shorting the virtual ground node. The proposed logic style also minimizes the dynamic portion of the power consumption due to short-circuit current by employing an enhanced self-timing buffer. Comparison results using a 80-nm CMOS technology show that STCML achieves 26 times reduction on leakage power consumption and 27% reduction on dynamic power consumption as compared to the conventional current-mode logic. They also indicate that up to 59% reduction on leakage power consumption compared to differential cascode voltage switch logic (DCVS).