• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.37-41
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• 2012

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.

• Journal of the Korean Vacuum Society
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• v.7 no.3
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• pp.167-272
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• 1998

The fluorine doped silicon oxide (SiOF) intermetal dielectric (IMD) films havc been of interest due to their lower dielectric constant and compatibility with existing process tools. However, instability issues related to hond and increasing dielectric constant due to water absorption when the SiOF film was exposured to atmospheric ambient. Therefore, the purpose nf this research is to study the effect of post oxygen plasma treatment on the resistance of nioisture absorption and reliability of SiOF film. Improvement of moisture ahsorption resistance of SiOF film is due to the forming of thin $SiO_2$ layer at the SiOF film surface. It is thought that the main effect of the improvement of moisture absorption resistance was densification of the top layer and reduction in the numher of Si-F honds that tend to associate with OH honds. However, the dielectric constant was inucased when plasma treatment time is above 5 min. In this study, therefore, it is thought that the proper plasma treatment time is 3 min when plasma treatment condition is 700 W of microwave power, 3 mTorr of process pressure and $300^{\circ}C$ of substrate temperature.

• Journal of the Korean Chemical Society
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• v.47 no.6
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• pp.608-613
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• 2003

In order to remove particles on surface of post-oxide CMP wafer, new cleaning solution was prepared by mixing with DHF (Diluted HF), nonionic surfactant PAAE (Polyoxyethylene Alkyl Aryl Ether), DMSO (Dimethylsulfoxide) and D.I.W.. Silicone wafers were intentionally contaminated by silica, alumina and PSL (polystylene latex) which had different zeta potentials in cleaning solution. This cleaning solution under megasonic irradiation could remove particles and metals simultaneously at room temperature in contrast to traditional AMP (mixture of $NH_4OH,\;H_2O_2$ and D.I.W) without any side effects such as increasing of microroughness, metal line corrosion and deposition of organic contaminants. This suggests that this cleaning solution would be useful future application with copper CMP in brush cleaning process as well as traditional post CMP cleaning process.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.7-12
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• 2018

The effects of Ru deposition temperature and post-annealing conditions on the interfacial adhesion energies of atomic layer deposited (ALD) Ru diffusion barrier layer and Cu thin films for the advanced Cu interconnects applications were systematically investigated. The initial interfacial adhesion energies were 8.55, 9.37, $8.96J/m^2$ for the sample deposited at 225, 270, and $310^{\circ}C$, respectively, which are closely related to the similar microstructures and resistivities of Ru films for ALD Ru deposition temperature variations. And the interfacial adhesion energies showed the relatively stable high values over $7.59J/m^2$ until 250h during post-annealing at $200^{\circ}C$, while dramatically decreased to $1.40J/m^2$ after 500 h. The X-ray photoelectron spectroscopy Cu 2p peak separation analysis showed that there exists good correlation between the interfacial adhesion energy and the interfacial CuO formation. Therefore, ALD Ru seems to be a promising diffusion barrier candidate with reliable interfacial reliability for advanced Cu interconnects.

• Korean Chemical Engineering Research
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• v.45 no.6
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• pp.633-637
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• 2007

Electroless plating of Co-alloy thin films as capping layers for Cu interconnection has been investigated using alkali-free precursors such as $(NH_4)_2Co(SO_4)_2{\cdot}6H_2O$, $(NH_4)_2WO_4$, $(NH_4)H_2PO_4$, etc. The characteristics of the Co-alloy thin films were discussed by analyses of the effects of pH, Co-precursor concentration, and deposition temperature on the thickness and surface morphology of the films. The thickness of the Co-alloy thin films increased with increasing pH, Co-precursor concentration, and deposition temperature, similarly to the results of electroless plating of Co-alloy thin films using alkali-containing chemicals. The SEM images of the surface of the Co-alloy thin films showed that the proper ranges of pH and deposition temperature were 8.5~9.5 and $75{\sim}85^{\circ}C$, respectively. This work found a feasibility that Co-alloy thin films as capping layers for Cu interconnection could be electroless plated using alkali-free chemicals.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.375-381
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• 2001

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide bit-line with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance tungsten bit-line fabrication process with various RTP(Rapid Thermal Process) temperature and additional ion implantation. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF$_2$ ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

• Journal of the Korean Vacuum Society
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• v.10 no.3
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• pp.361-367
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• 2001

Recently, Chemical Mechanical Polishing(CMP) has become a leading planarization technique as a method for silicon wafer planarization that can meet the more stringent lithographic requirement of planarity for the future submicron device manufacturing. The SOI(Silicon On Insulator) wafer has received considerable attention as bulk-alternative wafer to improve the performance of semiconductor devices. In this paper, the objective of study is to investigate Material Removal Rate(MRR) and surface micro-roughness effects of slurry and pad in the CMP process. When particle size of slurry is increased, Material Removal rate increase. Surface micro-roughness is greater influenced by pad than by particle size of slurry. As a result of AM measurement, surface micro-roughness was improved from 27 $\AA$ Rms to 0.64 $\AA$Rms.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1300-1303
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• 2004

Copper는 낮은 저항률과 높은 Electromigration 저항 때문에 반도체 소자에 배선 재료로 사용된다. CMP 공정을 이용 하여 Cu wafer의 여러 가지 특성을 파악하기에는 wafer의 소모량이 많고 고가가의 비용이 예상 되므로, 본 논문에서는 비용절감을 위하여 wafer를 Disc로 대체 하고자 실험을 진행 하였고 Cu wafer와 Disc의 비료 방법은 우선 PM-5 (Genitech. co) 장비를 이용하여 removal rate의 차이점을 알 아 보았으며, 서로의 etch rate을 reomval rate과 비교하였다. EG&G 273A를 통하여 Cu wafer와 disc의 corrosion potential과 $R_p$ (Polarization resistance)값을 서로 비교 하였다. 이 논문에서는 이러한 것들을 서로 비교 하여, Cu wafer와 disc에서의 상관관계를 알고자 하였으며, 만약에 Cu wafer와 disc의 특성이 비슷하다면, Cu wafer 대신에 disc를 이용 하여 실험하여도 되는지에 관하여 조사 하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.163-163
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• 2008

반도체 소자가 고집적화 되고 고속화를 필요로 하게 됨에 따라, 기존에 사용되었던 알루미늄이나 텅스텐보다 낮은 전기저항, 높은 electro-migration resistance으로 미세한 금속배선 처리가 가능한 Cu가 주목받게 되었다. 하지만 과잉 디싱 현상과 에로젼을 유도하여 메탈라인 브리징과 단락을 초래할 있고 Cu의 단락인 islands를 남김으로서 표면 결함을 제거하는데 효과적이지 못다는 단점을 가지고 있었다. 특히 평탄화 공정시 높은 압력으로 인하여 Cu막의 하부인 ILD막의 다공성의 low-k 물질의 손상을 초래 할 수 있는 문제점을 해결하기 위하여 기존의 CMP에 전기화학을 결합시킴으로서 낮은 하력에서의 Cu 평탄화를 달성 할 수 있는 기존의 CMP 기술에 전기화학을 접목한 새로운 개념의 ECMP (electrochemical-mechanical polishing) 기술이 생겨나게 되었다. 따라서 본 논문에서는 최적화된 ECMP 공정을 위하여 I-V곡선과 CV법을 이용하여 active. passive. trans-passive 영역의 전기화학적 특징을 알아보았고. Cu막의 표면 형상을 알아보기 위해 Scanning Electron Microscopy (SEM) 측정과 Energy Dispersive Spectroscopy (EDS) 분석을 통해 금속 화학적 조성을 조사하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.82-90
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• 2011

An accurate signal integrity verification method based on high-frequency measurements is proposed. For practical transmission lines that require a package process, process variations metal roughness and skin effects and boundary conditions may have deteriorative effects on circuit performance. These effects are represented in terms of parameters that can be readily utilized for field-solver. Thereby a more accurate signal integrity verification using field-solver can be achieved. It is shown that in both single and coupled lines the signal transients using the proposed method have excellent agreement with the measurement data.