• Journal of Korea Game Society
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• v.9 no.2
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• pp.135-142
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• 2009

Mesh denoising is a method to remove noise applying various filters. However, those methods usually spend much time since filtering is performed on CPU. Because GPU is specialized for floating point operations and faster than CPU, real-time processing for complex operations is possible. Especially mesh denoising is adequate for GPU parallel processing since it repeats the same operations for vertices or triangles. In this paper, we propose mesh denoising algorithm based on bilateral filtering using GPU parallel processing to reduce processing time. It finds neighbor triangles of each vertex for applying bilateral filter, and computes its normal vector. Then it performs bilateral filtering to estimate new vertex position and to update its normal vector.

• The KIPS Transactions:PartC
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• v.18C no.1
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• pp.1-6
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• 2011

The performance and practicality of cryptosystem for encryption, decryption, and primality test is primarily determined by the implementation efficiency of the modular exponentiation of $a^b$(mod n). To compute $a^b$(mod n), the standard binary squaring still seems to be the best choice. But, the d-ary, (d=2,3,4,5,6) method is more efficient in large b bits. This paper suggests m-numeral system modular exponentiation. This method can be apply to$b{\equiv}0$(mod m), $2{\leq}m{\leq}16$. And, also suggests the another method that is exit the algorithm in the case of the result is 1 or a.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.07a
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• pp.444-446
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• 2015

컴퓨터 생성 홀로그램(CGH: computer generated hologram) 기법은 기존의 홀로그램의 광학적 장치의 단점을 보완하여 범용 컴퓨터에서 홀로그램을 생성할 수 있도록 하는 기술이다. CGH는 입력으로 주어지는 물체의 3차원 정보와 출력으로 나오는 디지털 홀로그램의 해상도에 따라 그 연산량이 결정 된다. CGH는 단순하고 반복적인 수학적 계산을 통하여 디지털 홀로그램을 생성하게 되는데, 기존의 연구들에서는 GPU(graphic processing unit)를 이용하여 알고리즘들을 병렬적으로 처리한다. 본 논문에서는 기존연구에서 쓰인 GPU를 이용한 CGH을 개선하여 GPU가 장착되지 않은 상용 컴퓨터에서 GPU가 장착된 다른 컴퓨터들의 연산 자원을 활용하여 CGH를 수행 할 수 있는 프로그램의 개발 방법을 제안 한다. 본 시스템은 GPU가 요구되지 않는 한 개의 서버 컴퓨터와 GPU가 장착된 다수의 클라이언트들로 구성되어 있다. 서버 측에서 물체의 3차원 정보를 입력 받아 각각의 클라이언트들에게 적절한 연산량을 분배하고, 각 클라이언트들은 이미 알려진 GPU 기반 CGH를 통하여 연산을 수행 한 뒤, 그 결과를 서버로 다시 전송하게 된다. 서버는 수신한 각 결과들을 누적하여 입력 받은 물체에 대한 하나의 온전한 홀로그램을 생성할 수 있게 된다.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.36-41
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• 2016

LDPC code has beend applied in recent communication standards, such as Wi-Fi, WiGig, 10GBased-T Ethernet as a forward error correction code. However, LDPC code is required a large amount of computational complexity due to large iterations and block lengths for high performances. To solve this problem, various research has been continously performed for reducing computational complexity. In this paper, we propose AFC algorithm to deactive the variable and check node for reduce the computational complexity.

• Journal of Korea Game Society
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• v.12 no.4
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• pp.23-31
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• 2012

The collision processing is one of the essential factors to realize physical principles in the game, and it gives liveliness to the game. The collision processing requires a large amount of operations, and significantly affects the game performance. To address this problem, many studies have been conducted to reduce the operation volume, and the SAP algorithm is being widely used. However, its efficiency is low because it involves repetitive operations. In this study, a distance-based SAP algorithm was proposed to reduce the operation volume for the collision processing and address the problem of the SAP algorithm. A test was conducted to measure the FPS using the simulation program, which was developed with the proposed algorithm. The FPS was 2-33 times higher with the proposed algorithm, which indicated that the efficiency of the collision processing was improved.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.1107-1111
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• 2005

The DVR system realization with watermarking and MPEG-4 for real time processing speed improvement is presented in this paper. For the real time processing the system is used the DSP processor, Quick DMA for data transmission, watermarking for security and MPEG-4 compression for facility. The algorithms are that the operational structure has the internal memory of processor, and the optimal realization is suitable to form the DSP processor structure r processed for the iterative operations. The experimental result shows the real time processing is improved 12% over for the D1 image in comparison with the other system.

• Journal of IKEEE
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• v.18 no.2
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• pp.272-281
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• 2014

In electrical impedance tomography (EIT), modified Newton Raphson (mNR) method is widely used inverse algorithm for static image reconstruction due to its convergence speed and estimation accuracy. The unknown conductivity distribution is estimated iteratively by minimizing a cost functional such that the residual error namely the difference in measured and calculated voltages is reduced. Although, mNR method has good estimation performance, EIT inverse problem still suffers from ill-conditioned and ill-posedness nature. To mitigate the ill-posedness, generally, regularization methods are adopted. The inverse solution is highly dependent on the choice of regularization parameter. In most cases, the regularization parameter has a constant value and is chosen based on experience or trail and error approach. In situations, when the internal distribution changes or with high measurement noise, the solution does not get converged with the use of constant regularization parameter. Therefore, in this paper, in order to improve the image reconstruction performance, we propose a new scheme to determine the regularization parameter. The regularization parameter is computed based on residual error and updated every iteration. The proposed scheme is tested with numerical simulations and laboratory phantom experiments. The results show an improved reconstruction performance when using the proposed regularization scheme as compared to constant regularization scheme.

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.974-984
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• 1995

This paper presents a design of a high performance MULVEC (MULtithreaded architecture for the VEctor Computations), as a building block of massively parallel Processing systems. The MULVEC comes from the synthesis of the dataflow model and the extant super sclar RISC microprocesso r. The MULVEC reduces, using status fields, the number of synchronizations in the case of repeated vector computations within the same thread segment, and also reduces the amount of the context switching, network traffic, etc. After be nchmark programs are simulated on the SPARC station 20(super scalar RISC microprocessor)the performance (execution time of programs and the utilization of processors) of MULVEC and the performance(execution time of a program) of *Taccording the different numbers of node are analyzed. We observed that the execution time of the program in MULVEC is faster than that in * T about 1-2 times according the number of nodes and the number of the repetitions of the loop.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.3
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• pp.70-79
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• 2007

H.264/AVC has many repeated computation for motion estimation. Because of that, it takes much time to encode and it is very hard to implement into a real-time encoder. Many fast algorithms were proposed to reduce computation time but encoding quality couldn't be qualified. In this paper we proposed a new motion vector prediction method for efficient and fast full search H.264/AVC motion estimation. We proposed independent motion vector prediction and SAD share for motion estimation. Using our algorithm, motion estimation reduce calculation complexity 80% and less distortion of image (less PSNR drop) than previous full search scheme. We simulated our proposed method. Maximum Y PSNR drop is about 0.04 dB and average bit increasing is about 0.6%.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.12
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• pp.391-398
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• 2015

This paper devises a performance improvement and evaluation process of circuit minimization algorithms for mentorship education of distinguished informatics gifted secondary students. In the process, students learn that there are several alternative equivalent circuits for a target function and recognize the necessity for formalized circuit minimization methods. Firstly, they come at the concept of circuit minimization principle from Karnaugh Map which is a manual methodology. Secondly, they explore Quine-McCluskey algorithm which is a computational methodology. Quine-McCluskey algorithm's time complexity is high because it uses set operations. To improve the performance of Quine-McCluskey algorithm, we encourage them to adopt a bit-wise data structure instead of integer array for sets. They will eventually see that the performance achievement is about 36%. The ultimate goal of the process is to enlarge gifted students' interest and integrated knowledge about computer science encompassing electronic switches, logic gates, logic circuits, programming languages, data structures and algorithms.