• Transactions of the Korean hydrogen and new energy society
• /
• v.31 no.5
• /
• pp.480-488
• /
• 2020

This study was conducted to improve the flow uniformity inside the chip tester through changing the flow path formation according to the inlet and outlet position of chamber. The internal flow and velocity distributions of the modified chamber models (Cases 1-3) were compared with the reference chamber model through three-dimensional Reynolds-averaged Navier-Stokes equations with k-ε turbulence model. The modified chamber models showed the superior flow uniformity characteristics compared to the reference chamber model. To investigate the flow uniformity in the chip tester, the standard deviation of the velocity was defined and compared. Through the internal flow analysis and assesment of the standard deviation, Case 2 among the test cases including the reference model showed the best flow uniformity generally.

• Journal of the Semiconductor & Display Technology
• /
• v.8 no.4
• /
• pp.53-58
• /
• 2009

A SMT mounter is a kind of equipment that mounts SMD parts quickly on the printed circuit board. By using linear motors, it is controlled with high speed and precision, which is similar to semi-conductor and display process equipment. It is necessarily used in an assembly process of an electronic device. Mobile devices such as a mobile phone and PDA are required to reduce mount areas due to the demands for high performance and small size. Hence, super small sized and complex mobile devices have been developed. To improve the productivity of the corresponding equipment, designs with large sized, high speed, and multidisciplinary functions have been consistently performed. Meanwhile, a design trend of large size and light-weight on SMT mounter causes a low natural frequency of systems and vibration problems at the high speed operation. In this paper, the dynamic characteristics of the SMD mounter system were investigated through a modal test and transmissibility test, and verified by finite element method. Also, various design improvement was performed to avoid the resonance phenomena.

• Journal of the Semiconductor & Display Technology
• /
• v.3 no.3
• /
• pp.11-17
• /
• 2004

This research has been progressed for adhesive improvement of the Polyimide/Buffer layer/Cu at the COF(Chip On Film) which induced as the alternative plan about high concentration of a circuit or substrates according to demands of miniaturization and high efficiency of various electronic equipment. RF plasma equipment was applied to when plama pretreatment was performed for improvement of adhesive strength of PI and Cr as the buffer layer. Experimental fluents were a species of the buffer layer, depositied time and the ratio of $O_2$/Ar when performed to plasma pretreatment. The results are that Ni was superior to Cr at peel test according to a species of the buffer layer, peel strength and Cu THK were showed proportional relation to deposition structure of the same buffer layer and sample of the Cr depositied time(30 sec) and Cu depositied time(20 min) was showed good adhesion to peel test according to Cr's depositied time and Cu's depositied time. When perform PI's plasma pretreatment peel strength and $O_2$/Ar ratio were showed proportional relation. But $O_2$/Ar(2/5) was best condition since then decreased.

• Journal of the Semiconductor & Display Technology
• /
• v.22 no.1
• /
• pp.1-5
• /
• 2023

Most of the production process is performed in a cleanroom in the case of facilities that produce semiconductor chips or display panels. Therefore, environmental management of cleanrooms is very important for product yield and quality control. Among them, airborne particles are a representative management item enough to be the standard for the actual cleanroom rating, and it is a part of the Fab or Facility monitoring system, and the sequential particle monitoring system is mainly used. However, this method has a problem in that measurement efficiency decreases as the length of the sampling tube increases. In addition, a statistically significant test of deterioration in efficiency has rarely been performed. Therefore, in this study, the statistically significant test between the number of particles measured by InSitu and the number of particles measured for each sampling tube ends(Remote). Through this, the efficiency degradation problem of the sequential particle monitoring system was confirmed by a statistical method.

• Journal of the Semiconductor & Display Technology
• /
• v.5 no.2 s.15
• /
• pp.33-36
• /
• 2006

Many issues arose to use the Pb-free solder as adhesive materials in MEMS ICs and packaging. Then this study for easy and simple sealing method using adhesive materials was carried out to maintain hermetic characteristic in MEMS Package. In this study, Hermetic characteristic using negative PR (XP SU-8 3050 NO-2) as adhesive at the interface of Si test coupon/glass substrate and Si test coupon/LTCC substrate was examined. For experiment, the dispenser pressure was 4 MPa and the $200\;{\mu}m{\Phi}$ syringe nozzle was used. 3.0 mm/sec as speed of dispensing and 0.13 mm as the gap between Si test coupon and nozzle was selected to machine condition. 1 min at $65^{\circ}C$ and 15 min at $95^{\circ}C$ as Soft bake, $200\;mj/cm^2$ expose in 365 nm wavelength as UV expose, 1 min at $65^{\circ}C$ and 6 min at $95^{\circ}C$ as Post expose bake, 60 min at $150^{\circ}C$ as hard bake were selected to activation condition of negative PR. Hermetic sealing was achieved at the Si test coupon/ glass substrate and Si test coupon/LTCC substrate. The leak rate of Si test coupon/glass substrate was $5.9{\times}10^{-8}mbar-l/sec$, and there was no effect by adhesive method. The leak rate of Si test coupon/LTCC substrate was $4.9{\times}10^{-8}mbar-l/sec$, and there was no effect by dispensing cycle. Better leak rate value could be achieved to use modified substrate which prevent PR flow, to increase UV expose energy and to use system that controls gap automatically with vision.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.15 no.11
• /
• pp.6821-6829
• /
• 2014

The use of semiconductor devices as a component of eco-friendly motor vehicles has increased and their widespread use as high voltage switches is expected. On the other hand, in the case of high-voltage switches, reliability test equipment is not localized. To test high voltage switches, this paper analyzed the relevant test standards for developing power supplies. In particular, for the automotive semiconductor reliability test, the AEC (Automotive Electronic Council) Q101 was analyzed. Based on that, the standard specifications of the power supply were determined. For the main power circuit, the pull bridge converter was adopted and based on the specification, the circuit parameters were determined and verified by simulation. The interface for the parallel and pattern operation was designed. The characteristics of the power supply were tested.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.10
• /
• pp.3226-3235
• /
• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2012.11a
• /
• pp.123-123
• /
• 2012

최근 연구되고 있는 TSV(Through Silicon Via) 기술은 Si 웨이퍼 상에 직접 전기적 연결 통로인 관통홀을 형성하는 방법으로 칩간 연결거리를 최소화 할 수 있으며, 부피의 감소, 연결부 단축에 따른 빠른 신호 전달을 가능하게 한다. 이러한 TSV 기술은 최근의 초경량화와 고집적화로 대표되는 전자제품의 요구를 만족시킬 수 있는 차세대 실장법으로 기대를 모으고 있다. 한편, 납땜 재료의 주 원료인 주석은 주로 반도체 소자의 제조, 반도체 칩과 기판의 접합 및 플립 칩 (Flip Chip) 제조시의 범프 형성 등 반도체용 배선재료에 널리 사용되고 있다. 최근에는 납의 유해성 때문에 대부분의 전자제품은 무연솔더를 이용하여 제조되고 있지만, 주석을 이용한 반도체 소자가 고밀도화, 고 용량화 및 미세피치(Fine Pitch)화 되고 있기 때문에, 반도체 칩의 근방에 배치된 주석으로부터 많은 알파 방사선이 방출되어 메모리 셀의 정보를 유실시키는 소프트 에러 (Soft Error)가 발생되는 위험이 많아지고 있다. 이로 인해, 반도체 소자 및 납땜 재료의 주 원료인 주석의 고순도화가 요구되고 있으며, 특히 알파 방사선의 방출이 낮은 로우알파솔더 (Low Alpha Solder)가 요구되고 있다. 이에 따라 본 연구는 4인치 실리콘 웨이퍼상에 직경 $60{\mu}m$, 깊이 $120{\mu}m$의 비아홀을 형성하고, 비아 홀 내에 기능 박막증착 및 전해도금을 이용하여 전도성 물질인 Cu를 충전한 후 직경 $80{\mu}m$의 로우알파 Sn-1.0Ag-0.5Cu 솔더를 접합 한 후, 접합부 신뢰성 평가를 수행을 위해 고속 전단시험을 실시하였다. 비아 홀 내 미세구조와 범프의 형상 및 전단시험 후 파괴모드의 분석은 FE-SEM (Field Emission Scanning Electron Microscope)을 이용하여 관찰하였다. 연구 결과 비아의 입구 막힘이나 보이드(Void)와 같은 결함 없이 Cu를 충전하였으며, 고속전단의 경우는 전단 속도가 증가할수록 취성파괴가 증가하는 경향을 보였다. 본 연구를 통하여 전해도금을 이용한 비아 홀 내 Cu의 고속 충전 및 로우알파 솔더 볼의 범프 형성이 가능하였으며, 이로 인한 전자제품의 소프트에러의 감소가 기대된다.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.32 no.5
• /
• pp.212-217
• /
• 2022

Large thermal stress due to the difference between silicon carbide and graphite's coefficients of thermal expansion could be formed during crystal growing process of silicon carbide (SiC) at high temperature. The large thermal stress could separate the SiC seed crystals from graphite components, which bring about the drop of the seed crystal during crystal growth. However, the bonding properties of SiC seed crystal module has hardly reported so far. In this study, SiC and graphite were bonded using 3 types of bonding agents and a three-point bending tests using a mixed-mode flexure test were conducted for the bonded samples to evaluate the bonding characteristics between SiC and graphite. Raman spectroscopy, X-ray Photoelectron Spectroscopy, and X-ray Computed Tomography were used to analyze the bonding characteristics and the microstructures of the SiC-graphite interfaces bonded with the bonding agents. As results, an excellent bonding agent was chosen to fabricate SiC seed crystal module with 50 mm in diameter. An SiC single crystal with 50 mm in diameter was successfully grown without falling out during top seeded solution growth of SiC at high temperature.

• Journal of the Korean Vacuum Society
• /
• v.17 no.3
• /
• pp.175-182
• /
• 2008

This study is concerned with the evaluation of the corrosion resistance of coated semiconductor equipment parts with various processes. To select the appropriate basis for evaluation, replacement parts were observed during the semiconductor manufacturing process. This study also ran a dry corrosion test using $Al_2O_3$, which is mostly used as a coating material. This test quantitatively measured the efficiency of coated parts. Surface morphology, leakage current and breakdown voltage were also evaluated. This study showed that a dry corrosion process led to the drop of electrical properties, for example, the leakage current increase and the dielectric strength decrease. The surface morphology test displayed that surface damage is largely dependent on the exposure time to corrosive environments. By using the values that changed during the corrosion process, it may be possible to contrive a method to evaluate the efficiency of coated parts with various processes.