• Proceedings of the Korean Operations and Management Science Society Conference
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• 2001.10a
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• pp.298-301
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• 2001

In semiconductor manufacturing, wafer fabrication is the most complicated and important process, which is composed of several hundreds of process steps and several hundreds of machines involved. The productivity of the manufacturing mainly depends on how well they control balance of WIP flow to achieve maximal throughput under short manufacturing cycle time. In this paper mathematical formulation is suggested for the stepper scheduling, in which cycle time reduction and maximal production is achieved.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.1245-1248
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• 2012

반도체와 LCD 산업분야, 나노급 공정 및 검사기술이 요구되는 산업분야의 수요증가에 따라 초정밀 가공/생산/검사 장비를 설치, 운용하는 FAB. 구조물의 설계요구가 증대되고 있으며, 건물의 환경진동 규제치도 강화되고 있는 실정이다. 이와 같은 대형 구조물에서의 서브 마이크로 수준의 미진동(微振動)을 제어하는 문제는 진동 응답을 결정하는 구조와 재료가 복잡하고 다양한 형태를 갖고 있는 반면, 다루어야 할 동적 응답은 극한적으로 작은 마이크로 이하의 값을 다루어야 하기 때문에 매우 어렵다. 따라서 기존에 이용되고 있는 해석과 실험의 결과만으로는 신모델 설계에 적용하기 어렵다. 따라서, 본 논문에서는 실험적 데이터와 경험적 데이터들을 기반으로 구축된 데이터베이스를 이용하여 새로운 초정밀 FAB. 동적 구조 설계 시스템을 구현한다.

• Journal of the Korea Society for Simulation
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• v.21 no.2
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• pp.41-50
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• 2012

In this study we first explain details of the semiconductor manufacturing processes and cluster tools. Then we discuss the problems in current fab layout and cluster tool architecture. As a solution to these problems, we propose the ILE (In-Line EFEM) architecture in which wafer movements are conducted through interconnected EFEMs (Equipment Front End Modules) instead of AMHS (Automated Material Handling System). Then we model the pilot ILE system using discrete event simulation and analyze the cycle time. Finally we compare three different scenarios of equipment layout in the ILE system in terms of cycle time.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.868-871
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• 2012

반도체와 LCD 산업 분야, 나노급 공정 및 검사 기술이 요구되는 산업 분야의 수요 증가에 따라 초정밀 가공/생산/검사 장비를 설치, 운용하는 FAB. 구조물의 설계 요구가 층증대 되고 있다. 이에 따라 건물의 환경진동 규제치도 강화되고 있는 실정이다. 이와 같은, 대형 구조물에서 서브마이크로 수준의 미진동(微振動)을 제어하는 문제는 여전히 어려운 과제로 남아 있다. 이는 진동 응답을 결정하는 구조와 재료가 복잡하고 다양한 형태를 갖고 있는 반면, 다루어야 할 동적 응답은 극한적으로 작은 마이크로(micro) 이하의 값을 다루어야 한다. 그러므로, 기존에 이용되고 있는 해석과 실험의 결과만으로는 신모델 설계에 적용하는 것은 어렵다. 따라서, 본 논문에서는 이러한 영역의 경험적 데이터물을 체계적인 데이터베이스로 구축하여 새로운 동적 구조 설계 기술의 기반을 제공하고자 한다.

• Proceedings of the KAIS Fall Conference
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• 2010.11b
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• pp.555-558
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• 2010

차세대 반도체 산업은 제조공정의 미세화, 복잡화, 다단계화 등이 심화되고 이로 인해 제조원가의 절감을 위한 단위 Wafer당 보다 많은 칩을 생산할 수 있는 450mm 웨이퍼의 도입을 반드시 필요로 한다. 본 논문에서는 클러스터 툴을 주로 사용하는 450mm 웨이퍼 수율관리 개선 시스템의 구현방향과 상세 기능과 각 모듈에 대한 연구를 수행하였으며, 450mm 웨이퍼 생산체제 하에서 필요한 수율관리시스템인 RTFMD 시스템을 제안 하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.83.1-83.1
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• 2013

반도체 미세화, Glass 대면적화에 따른 산포관리 및 불량방지 필요(공정이격관리), 설비 데이터만으로는 Sensitivity가 낮아 공정 관리 어려움에 따른 대안 필요, 향후 추가 센서에 대한 접목이 용이한 SW Frame 필요, 양산적용을 위한 설비 및 FAB Host의 자동화 연계 개발 필요, 이종데이터의 통합를 통한 최적의 진단 및 관리가 필요합니다(SCM:툴박스). 즉, 기존의 장비 Parameter가 아닌 실제 공정시 Chamber로부터 얻을 수 있는 물리, 전기, 화학적인 데이터를 적합한 이종(異種) 센서를 직접 부착하여 이들 데이터를 통합 관리 분석 및 실시간 Monitoring을 통한 공정 진단 및 실시간 진단을 실행하는 솔루션입니다. 실 공정 시 적용이 유리한 OES 데이터를 주요 인자로 이외의 기타 데이터를 추가로 통합하여 특화된 분석환경과 공정 모니터링을 통하여 TAT (Turn Around Time)를 줄이고, MTBC (Mean Time Between Clean)를 늘림으로써 궁극적으로 칩메이커의 제품의 가격 경쟁력을 확보 할 수 있는 기능이며, 설비사 입장에서는 자사설비의 지능형 시스템을 위한 제반 기술이기도 합니다.

• Journal of the Korea Society for Simulation
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• v.11 no.3
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• pp.59-65
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• 2002

Semiconductor wafer fabrication is a business of high capital investment and fast changing nature. To be competitive, the production in a fab needs to be effectively planned and scheduled starting from the ramping up phase, so that the business goals such as on-time delivery, high output volume and effective use of capital intensive equipment can be achieved. Project executed that use conveyor in bay semiconductor A line. But conveyor capability is lacking and rundown happened in equipment. Do design without normal simulation and conveyor system failed. The comparison is peformed through simulation using .AutoMod a window 98 based discrete system simulation software, as a tool for comparing performance of proposed layouts. In this research estimate optimum conveyor capability, there is the purpose.

• Journal of the Korean Vacuum Society
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• v.17 no.4
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• pp.278-291
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• 2008

For the semiconductor manufacturing processes, so many vacuum systems are needed with large power consumption for vacuum pumps. Semiconductor device manufacturing makers are concerned about the power consumption and have to address this because it is related with the environmental issues. So many solutions including the design and the control of them by vacuum pump manufacturers to reduce the power consumption of vacuum pump are proposed. However, how to use vacuum pumps by users and the conditions for vacuum pump to be used are also very important to reduce the power consumption. In this article, how to reduce the power consumption of vacuum pumps is explained briefly and what the impact of semiconductor technology trend on the power consumption is considered very briefly.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.9 no.2
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• pp.87-95
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• 2014

The High-price development & testing tools and IP infratstructures are required for the development of system semi-conductors, but SMEs have not ability to prepare for them. Recently in terms of the miniaturization and the advancement of semiconductor process, the cost of the semi-conductor development have shown the rising tendency and the market-based design tools used are requied to be upgraded due to the advancement in the environment and technology. On the contray, many other contries such as Taiwan, Japan, China, and User are supporting this system semi-conductor industry. Korean government is trying to build the research infrastructure for system semi-conductor industry that aims to reduce the costs of the design infrastructure investment, to support the companies of system semi-conductor development and to incubate the fab-less start-ups. This study analyzes the feasibility of the project, by using the AHP analysis and the results shows that this project is considered feasible because the AHP overall score is evaluated as 0.840, the overall score is greater than or equal to 0.55.

• Journal of Korean Society of Occupational and Environmental Hygiene
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• v.26 no.1
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• pp.1-10
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• 2016

Objectives: The aim of this study is to review the results of exposure to chemicals and to extremely low frequency(ELF) magnetic fields generated in wafer fabrication operations in the semiconductor industry. Methods: Exposure assessment studies of silicon wafer fab operations in the semiconductor industry were collected through an extensive literature review of articles reported until the end of 2015. The key words used in the literature search were "semiconductor industry", "wafer fab", "silicon wafer", and "clean room," both singly and in combination. Literature reporting on airborne chemicals and extremely low frequency(ELF) magnetic fields were collected and reviewed. Results and Conclusions: Major airborne hazardous agents assessed were several organic solvents and ethylene glycol ethers from Photolithography, arsenic from ion implantation and extremely low frequency magnetic fields from the overall fabrication processes. Most exposures to chemicals reported were found to be far below permissible exposure limits(PEL) (10% < PEL). Most of these results were from operators who handled processes in a well-controlled environment. In conclusion, we found a lack of results on exposure to hazardous agents, including chemicals and radiation, which are insufficient for use in the estimation of past exposure. The results we reviewed should be applied with great caution to associate chronic health effects.