• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.119-126
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• 2012

H.264/AVC can use three transforms depending on types of residual data which are to be coded. H.264/AVC always executes $4{\times}4$ DCT transform. In $16{\times}16$ intra mode only, $4{\times}4$ Hadamard transform for luma DC coefficients and $2{\times}2$ Hadamard transform for chroma DC coefficients are performed additionally. Quantization is carried out to achieve further data compression after transform coding is completed. In this paper, the hardware implementation for DCT transform, Hadamard transform and quantization is studied. Especially, the proposed architecture adopting the pipeline technique can output a quantized result per clock cycle after 33-clock cycle latency. The proposed architecture is coded in Verilog-HDL and synthesized using Xilinx 7.1i ISE tool. The operating frequency is 106MHz at SPARTAN3S-1000. The designed IP can process maximum 33-frame at $1920{\times}1080$ HD resolution.

• Journal of Broadcast Engineering
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• v.2 no.2
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• pp.114-124
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• 1997

In object based coding, binary shape ccx:ling plays an important role by ccx:ling the outer shape of object. Here we propose a new shape ccx:ling tool, which enccx:les the outline of shape from a baseline. Different from 2-D (Vertex) shape ccx:ling algorithms. the proposed method encodeds the data that are extracted in a I-D fashion. The enccx:led data consist of the starting position, distance lists, and turning point lists. In the lossless ccx:ling mode, every contour pixel is input for ccx:ling, whereas variable sampling has been employed to enccx:le fewer contour pixels while preserving reasonable distortion. For interframe ccx:ling, a fast motion compensation was achieved by use of distance and turning point lists. Subjective viewing tests proved that the proposed method outperforms the current shape ccx:ling standard, CAE, in MPEG-4. In objective results for compression efficiency, the proposed method was significantly better in intraframe coding than CAE, whereas CAE was better in interframe ccx:ling.

• Journal of Advanced Marine Engineering and Technology
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• v.41 no.1
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• pp.76-82
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• 2017

Since the introduction of electronically controlled engines and electric propulsion ships, the need for an uninterruptible power supply for emergency power supply devices that use batteries has gained importance. The bidirectional converter in such emergency power supply devices is a crucial component. This paper proposes, a topology for an improved DC-DC bidirectional converter that is characterized by a high voltage conversion ratio and low voltage stress of switches. To confirm the performance of the converter, a computer simulation was executed with PSIM software. The conversion ratio of the proposed converter was found to be four times higher than the conventional boost converter in step-up mode and one-fourth that of the conventional buck converter in step-down mode, and the voltage stress of the switches was one-fourth of the high-side voltage. Moreover, the proposed converter was confirmed to be able to distribute equal currents between two interleaved modules without using any extra current-sharing control method because of the charge balance of its blocking capacitors.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.7
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• pp.785-790
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• 2008

In this paper, a new balun is proposed. This proposed balun has a DGS(Defected Ground Structure) pattern on the ground plane. The transmission-line is transformed by microstrip-to-slotline transition. DGS pattern on the ground plane and transition of the lines can be easily made a property of the balun. Resonance frequency of the DGS leads to operating frequency of the balun. Also the transition produces $180^{\circ}$ out-of-phase between two output ports without additional transmission line. In this paper, a new balun with VPDGS(Vertically Periodic Defected Ground Structure) effectively lower the operating frequency. To validate the proposed design method, the new balun is designed, fabricated and measured at 2 GHz.

• Journal of IKEEE
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• v.17 no.3
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• pp.267-274
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• 2013

This paper presents a design of LLC resonant converter IC for LED backlight unit based on PFM/PWM dual-mode feedback. Dual output LLC resonant architecture with a single inductor is proposed, where the master output is controlled by the PFM and slave output is controlled by the PWM. To regulate the master output PFM is used as feedback to control the frequency of the power switch. On the other hand, PWM feedback is used to control the pulse width of the power switch and to regulate the slave output. This chip is fabricated in 0.35um 2P3M BC(Bipolar-CMOS-DMOS) Process and the die area is $2.3mm{\times}2.2mm$. Current consumptions is 26mA from 5V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.51-57
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• 2010

A dual-mode direct conversion receiver is developed in $0.13\;{\mu}m$ RF CMOS process for IEEE 802.11n based wireless LAN and IEEE 802.16e based mobile WiMAX application. The RF receiver covers the frequency band between 2.3 and 2.7 GHz. Three-step gain control is realized in LNA by using current steering technique. Current bleeding technique is applied to the down-conversion mixer in order to lower the flicker noise. A frequency divide-by-2 circuit is included in the receiver for LO I/Q differential signal generation. The receiver consumes 56 mA at 1.4 V supply voltage including all LO buffers. Measured results show a power gain of 32 dB, a noise figure of 4.8 dB, a output $P_{1dB}$ of +6 dBm over the entire band.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.2
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• pp.106-112
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• 2007

This paper proposes a hybrid architecture algorithm for fast computation of DCT and DFT via recursive factorization. Recursive factorization of DCT-II and DFT transform matrix leads to a similar architectural structure so that common architectural base may be used by simply adding a switching device. Linking between two transforms was derived based on matrix recursion formula. Hybrid acrchitectural design for DCT and DFT matrix decomposition were derived using the generation matrix and the trigonometric identities and relations. Data flow diagram for high-speed architecture of Cooley-Tukey type was drawn to accommodate DCT/DFT hybrid architecture. From this data flow diagram computational complexity is comparable to that of the fast DCT algorithms for moderate size of N. Further investigation is needed for multi-mode operation use of FFT architecture in other orthogonal transform computation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.3
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• pp.292-300
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• 2010

In this paper, we propose a RF front-end architecture based on hybrid conversion which is available to receive both broadband and multiband DVB-H receiver, and a multi-function circuit for implementing the RF front-end is fabricated. A multi-function circuit is operated as a sub-harmonic mixer mode in the case of receiving a broadband VHF/UHF band, which show a conversion loss of -10.0 dB, noise figure of 7.0 dB and IIP3 of 2.0 dBm. On the other hand, it is performed as a attenuation mode with a insertion loss of -10.0 dB in receiving a multiband, L-band.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.68-73
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• 2013

In this paper, we proposed a readout circuit of pulse waveform and rate for a U-health system to monitor health condition. For long-time operation without replacing or charging a battery, either pulse waveform or pulse rate is selected as the output data of the proposed readout circuit according to health condition of a user. The proposed readout circuit consists of a simple digital logic discriminator and a dual-mode ADC which operates in the ADC mode or in the count mode. Firstly, the readout circuit counts pulse rate for 4 seconds in the count mode using the dual-mode ADC. Health condition is examined after the counted pulse rate is accumulated for 1 minute in the discriminator. If the pulse rate is out of the preset normal range, the dual-mode ADC operates in the ADC mode where pulse waveform is converted into 10-bit digital data with the sampling frequency of 1 kHz. These data are stored in a buffer and transmitted by 620 kbps to an external monitor through a RF transmitter. The data transmission period of the RF transmitter depends on the operation mode. It is generally 1 minute in the normal situation or 1 ms in the emergency situation. The proposed readout circuit was designed with $0.11{\mu}m$ process technology. The chip area is $460{\times}800{\mu}m^2$. According to measurement, the power consumption is $161.8{\mu}W$ in the count mode and $507.3{\mu}W$ in the ADC mode with the operating voltage of 1 V.

• Journal of Broadcast Engineering
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• v.16 no.3
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• pp.448-461
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• 2011

H.264/AVC significantly outperforms the previous video coding standards with many new coding tools. Among these tools, several intra-block coding tools can particularly improve coding efficiency. For intra prediction, H.264/AVC supports most probable mode in the entropy coding process to reduce syntax elements indicating intra prediction modes and most probable mode selection ratio is very high. Also, in general, natural images and videos have many homogeneous regions whose high correlation with neighbouring blocks. In this paper, we propose intra prediction mode SKIP mode using decoder-side prediction to improve the coding efficiency. The proposed method is determined the optimal prediction mode using only neighbouring block's information and coded on the basis of the conventional prediction/transform coding. And the prediction modes are not send to decoder at all. Skipped intra prediction mode is determined by decoder. Experimental results show that the proposed method achieves coding gains of 1.40% for common intermediate format(CIF), 3.24% for 720p sequences against the H.264/AVC JM 17.0 reference software.