• Journal of KIISE:Computer Systems and Theory
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• v.31 no.12
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• pp.704-715
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• 2004

Recently, a single or multi processor system uses the hierarchical memory structure to reduce the time gap between processor clock rate and memory access time. A cache memory system includes especially two or three levels of caches to reduce this time gap. Moreover, one of the most important things In the hierarchical memory system is the hit rate in level 1 cache, because level 1 cache interfaces directly with the processor. Therefore, the high hit rate in level 1 cache is critical for system performance. A victim cache, another high level cache, is also important to assist level 1 cache by reducing the conflict miss in high level cache. In this paper, we propose the advanced high level cache management scheme based on the processor reuse information. This technique is a kind of cache replacement policy which uses the frequency of processor's memory accesses and makes the higher frequency address of the cache location reside longer in cache than the lower one. With this scheme, we simulate our policy using Augmint, the event-driven simulator, and analyze the simulation results. The simulation results show that the modified processor reuse information scheme(LIVMR) outperforms the level 1 with the simple victim cache(LIV), 6.7% in maximum and 0.5% in average, and performance benefits become larger as the number of processors increases.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.7
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• pp.636-645
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• 2008

OneNAND flash is a high-performance hybrid flash memory that combines the advantages of both NAND flash and NOR flash. OneNAND flash has not only all virtues of NAND flash but also greatly enhanced read performance which is considered as a downside of NAND flash. As a result, it is widely used in mobile applications such as mobile phones, digital cameras, PMP, and portable game players. However, most of the general purpose operating systems, such as Linux, can not exploit the read performance of OneNAND flash because of the restrictions imposed by their virtual memory system and block I/O architecture. In order to solve that problem, we suggest a new approach called virtual I/O segment. By using virtual I/O segment, the superior read performance of OneNAND flash can be exploited without modifying the existing block I/O architecture and MTD subsystem. Experiments by implementations show that this approach can reduce read latency of OneNAND flash as much as 54%.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.476-487
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• 2007

Flash memory offers attractive features, such as non-volatile, shock resistance, fast access, and low power consumption for data storage. However, it has one main drawback of requiring an erase before updating the contents. Furthermore, flash memory can only be erased limited number of times. To overcome limitations, flash memory needs a software layer called flash translation layer (FTL). The basic function of FTL is to translate the logical address from the file system like file allocation table (FAT) to the physical address in flash memory. In this paper, a new FTL algorithm called an efficient and advanced space-management technique (EAST) is proposed. EAST improves the performance by optimizing the number of log blocks, by applying the state transition, and by using reallocation blocks. The results of experiments show that EAST outperforms FAST, which is an enhanced log block scheme, particularly when the usage of flash memory is not full.

• Journal of KIISE:Databases
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• v.37 no.6
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• pp.292-299
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• 2010

Recently, as flash memory is used as digital storage devices, necessity for digital forensics is growing in a flash memory area for digital evidence analysis. For this purpose, it is important to recover crashed files stored on flash memory efficiently. However, it is inefficient to apply the hard disk based file recovery techniques to flash memory, since hard disk and flash memory have different characteristics, especially flash memory being unable to in-place update. In this paper, we propose a flash-aware file recovery technique for digital forensics. First, we propose an efficient search technique to find all crashed files. This uses meta-data maintained by FTL(Flash Translation Layer) which is responsible for write operation in flash memory. Second, we advise an efficient recovery technique to recover a crashed file which uses data location information of the mapping table in FTL. Through diverse experiments, we show that our file recovery technique outperforms the hard disk based technique.

• Proceedings of the Korea Information Processing Society Conference
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• 2006.05a
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• pp.1337-1340
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• 2006

플래시 메모리는 비 휘발성, 경량화, 견고성, 빠른 속도 등의 장점을 가지고 있어 임베디드 시스템이나 모바일 기기를 위한 저장 장치로 각광 받고 있다. 그러나 데이터를 업데이트할 때 덮어쓰지 못하고, 지우고 다시 써야 하는 물리적 특성이나, 이 때 생기는 오버헤드, 데이터를 쓰는 횟수의 제한 같은 기술적 문제점이 있기 때문에 저장 장치로 대체되기 위해서는 파일 시스템과 플래시 메모리 사이에 FTL 을 두어 이를 해결해 주어야 한다. 본 논문에서는 데이터를 업데이트할 때 성능 향상을 위해 새로운 가비지 콜렉션 기법을 제안하고, 그 성능을 분석하였다. 플래시 메모리에 수행되는 요청이 존재하지 않을 때 thread 형태로 가비지 콜렉션을 수행하여 시스템의 유휴 시간을 활용하며 이 때 정리할 블록을 효과적으로 선정하여 메모리로의 요청이 없을 때는 최대한 많은 가용 블록을 획득하고 메모리의 요청이 빈번할 때에는 최대한 빨리 가용 블록을 획득할 수 있도록 하는 알고리즘을 제안하고 이를 구현하였다. 이를 사용하는 경우 필요할 때만 가비지 콜렉션을 수행하는 것보다 최대 25% 쓰기 시간을 줄일 수 있음을 확인하고, 시스템의 상황에 따라 블록을 선정하는 알고리즘을 유동적으로 변화시킴으로써 가비지 콜렉션의 성능을 향상시킬 수 있음을 확인하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.699-702
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• 2009

저 전력, 내구성, 소형, 빠른 속도 등의 장점을 가지고 있는 플래시 메모리는 생산 기술 발전에 힘입어 센서 노드, 휴대폰, MP3, PMP등의 소형 전자 제품의 저장장치에서부터 SSD형태로 노트북이나 서버에 이르기 까지 그 활용범위가 더욱 확장되어 가고 있다. 다양한 시스템에서 사용될 수 있는 플래시 메모리의 특성상 이에 저장된 데이터의 호환성은 중요한 고려사항이다. 이를 위해 플래시 메모리의 고유한 특성을 숨기고 일반적인 블록장치로 에뮬레이션 해주는 소프트웨어인 FTL과 FAT 파일시스템이 플래시 메모리 관리를 위한 사실상 표준 소프트웨어로써 사용되고 있다. 그러나 범용 컴퓨터를 기반으로 개발된 FTL과 FAT 파일시스템을 열악한 하드웨어로 구성된 시스템에서 구동하는 경우 많은 제약이 발생한다. 따라서 본 논문에서는 이러한 제약사항을 극복하기 위해 최소한의 파일시스템 기능을 제공하는 FAT 표준 호환 FTL을 제안한다. 제안된 기법은 리눅스 운영체제에 동적으로 적재 가능한 모듈형태로 구현되었으며, 실험을 통해 본 논문에서 제안한 기법이 기존 기법 대비 32%의 메모리 공간을 절약할 수 있으며, 동시에 완벽한 FAT 호환성을 제공함을 확인할 수 있었다.

• The KIPS Transactions:PartD
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• v.17D no.6
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• pp.383-394
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• 2010

Flash memory based SSDs are currently being considered as a promising candidate for replacing hard disks due to several superior features such as shorter access time, lower power consumption and better shock resistance. However, SSDs have different characteristics from hard disk such as difference of unit and time for read, write and erase operation and impossibility for over-writing. Because of these reasons, SSDs have disadvantages on hard disk based systems, so FTL(Flash Translation Layer) is designed to increase SSDs' efficiency. In this paper, we propose an advanced logical address mapping method for increasing SSDs' performance, which is named HAMM(Hybrid Address Mapping Method). HAMM addresses drawbacks of previous block-mapping method and super-block-mapping method and takes advantages of them. We experimented our method on our own SSDs simulator. In the experiments, we confirmed that HAMM uses storage area more efficiently than super-block-mapping method, given the same buffer size. In addition, HAMM used smaller memory than block-mapping method to construct mapping table, demonstrating almost same performance.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.197-199
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• 2012

Recently, a lot of general-purpose application programs in addition to graphic applications have been parallelized for boosting their performance using Graphic Processing Unit (GPU)'s excellent floating-point performance. In order to maximize the application performance on GPUs, optimizing the memory hierarchy and the on-chip caches such as the shared memory is essential. In this paper, we propose techniques to optimize the shared memory, and verify its effectiveness using a pattern matching application program.

• Journal of the Korea Society of Computer and Information
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• v.25 no.10
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• pp.125-133
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• 2020

In this paper, we design 4-layer TCP/IP that utilizes minimal memory and processor resources in Internet of Things(IoT) systems. The TCP/IP designed in this paper has the following characteristics. First, memory resource is minimized by using minimal memory allocation. Second, processor resource is minimized by using minimal memory copy. Third, the execution time of the TCP/IP can be completed in a deterministic time. Fourth, there is no memory leak problem. The standard in minimal resources for memory and processor derived in this paper can be used to check whether the network subsystems of the already implemented IoT systems are efficiently implemented. As the result of measuring the amount of memory allocation and copy of the network subsystem of Zephyr, an open source IoT kernel recently released by the Linux Foundation, we found that it was bigger than the standard in minimal resources derived in this paper. The network subsystem of Zephyr was improved according to the design proposed in this paper, confirming that the amount of memory allocation and copy were decreased by about 39% and 67%, respectively, and the execution time was also reduced by about 28%.

• Journal of the Korea Society of Computer and Information
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• v.15 no.8
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• pp.23-30
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• 2010

Flash memory is non-volatile and can retain data even after system is powered off. Besides, it has many other features such as fast access speed, low power consumption, attractive shock resistance, small size, and light-weight. As its price decreases and capacity increases, the flash memory is expected to be widely used in consumer electronics, embedded systems, and mobile devices. Flash storage systems generally adopt a software layer, called FTL. In this research, we proposed a new FTL mechanism for overcoming the major drawback of conventional block mapping algorithm. In addition to the block mapping table, a index block mapping table with a small size is used to indicate sector location. The proposed indexed block mapping algorithm by adding a small size. By the simulation result, the proposed FTL provides an enhanced speed than a conventional hybrid mapping algorithm by around 45% in average, and the requirement of mapping memory is also reduced by around 12%.