• Journal of Internet Computing and Services
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• v.6 no.4
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• pp.47-58
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• 2005

There are two major type of flash memory products, namely, NAND-type and NOR-type flash memory. NOR-type flash memory is generally deployed as ROM BIOS code storage because if offers Byte I/O and fast read operation. However, NOR-type flash memory is more expensive than NAND-type flash memory in terms of the cost per byte ratio, and hence NAND type flash memory is more widely used as large data storage such as embedded Linux file systems. In this paper, we designed an efficient flash memory file system based an Embedded system and presented to make up for reduced to Swapping a weak System Performance to flash file system using NAND-type flash memory, then proposed Swapping algorithm insured to an Execution time. Based on Implementation and simulation studies, Then, We improved performance bases on NAND-type flash memory to the requirement of the embedded system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.85-92
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• 2007

With the development of the memory design and process technology, the production of high-density memory has become a large scale industry. Since these memories require complicated designs and accurate manufacturing processes, It is possible to exist more defects. Therefore, in order to analyze the defects, repair them and fix the problems in the manufacturing process, memory repair using BISR(Built-In Self-Repair) circuit is recently focused. This paper presents an efficient memory BISR architecture that uses spare memories effectively. The proposed BISR architecture utilizes the additional storage space named 'sign bit' for the repair of memories. This shows the better performance compared with the previous works.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.5
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• pp.133-138
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• 2022

Recently, as GPU performance has improved in HPC and artificial intelligence, its use is becoming more common, but GPU programming is still a big obstacle in terms of productivity. In particular, due to the difficulty of managing host memory and GPU memory separately, research is being actively conducted in terms of convenience and performance, and various CPU-GPU memory transfer programming methods are suggested. Meanwhile, recently many SoC (System on a Chip) products such as Apple M1 and NVIDIA Tegra that bundle CPU, GPU, and integrated memory into one large silicon package are emerging. In this study, data between CPU and GPU devices are used in such an integrated memory device and performance-related research is conducted during transmission. It shows different characteristics from the existing environment in which the host memory and GPU memory in the CPU are separated. Here, we want to compare performance by CPU-GPU data transmission method in NVIDIA SoC chips, which are integrated memory devices, and NVIDIA SMX-based V100 GPU devices. For the experimental workload for performance comparison, a two-dimensional matrix transposition example frequently used in HPC applications was used. We analyzed the following performance factors: the difference in GPU kernel performance according to the CPU-GPU memory transfer method for each GPU device, the transfer performance difference between page-locked memory and pageable memory, overall performance comparison, and performance comparison by workload size. Through this experiment, it was confirmed that the NVIDIA Xavier can maximize the benefits of integrated memory in the SoC chip by supporting I/O cache consistency.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.1
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• pp.77-82
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• 2014

SD memory cards are widely used in portable digital devices, and most of them exploit NAND flash memory as their storage, so that they have a feature of storing users' important data safely with low costs. In case of using NAND flash memory as storage, however, there is no method to store users' data if memory capacity is insufficient when transferring a large volume of data. This paper proposes a virtual SD memory card system. It used a SD memory card device driver to process data requested from a host by exploiting external storage rather than by exploiting flash memory as a memory core for storing data to the SD memory card. For experiment, it used the FPGA-based SD card slave controller IP on the SMC controller with a S3C2450 ARM CPU to test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.72-85
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• 2007

The development of memory design and process technology enabled the production of high density memory. However, this increased the complexity of the memory making memory testing more complicated, and as a result, it brought about an increase in memory testing costs. Effective memory test algorithm must detect various types of defects within a short testing time, and especially in the case of port memory test algorithm, it must be able to detect single port memory defects, and all the defects in the dual port memory. The March A2PF algorithm proposed in this paper is an effective test algorithm that detects all types of defects relating to the duel port and single port memory through the short 18N test pattern.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.543-556
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• 2009

Recently, NAND flash memory is being used as the swap device of virtual memory as well as the file storage of mobile systems. Since temporal locality is dominant in page references of virtual memory, LRU and its approximated CLOCK algorithms are widely used. However, cost of a write operation in flash memory is much larger than that of a read operation, and thus a page replacement algorithm should consider this factor. This paper analyzes virtual memory read/write reference patterns individually, and observes the ranking inversion problem of temporal locality in write references which is not observed in read references. With this observation, we present a new page replacement algorithm considering write frequency as well as temporal locality in estimating write reference behaviors. This new algorithm dynamically allocates memory space to read/write operations based on their reference patterns and I/O costs. Though the algorithm has no external parameter to tune, it supports optimized implementations for virtual memory systems, and also performs 20-66% better than CLOCK, CAR, and CFLRU algorithms.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.683-695
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• 2007

NAND flash memory-based file systems cannot store their system-related information in the file system due to wear-leveling of NAND flash memory. This forces NAND flash memory-based file systems to scan the whole flash memory during their mounts. The mount time usually increases linearly according to the size of and the usage pattern of the flash memory. NAND flash memory has been widely used as the storage medium of mobile devices. Due to the fact that mobile devices have unstable power supply, the file system for NAND flash memory requires stable recovery mechanism from power failure. In this paper, we present design and implementation of a new NAND flash memory-based file system that provides fast mount and enhanced stability. Our file system mounts 19 times faster than JFFS2's and 2 times faster than YAFFS's. The stability of our file system is also shown to be equivalent to that of JFFS2.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.125-134
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• 2004

Recently, an on-chip compressed cache system was presented to alleviate the processor-memory Performance gap by reducing on-chip cache miss rate and expanding memory bandwidth. This research Presents an extended on-chip compressed cache system which also significantly expands main memory capacity. Several techniques are attempted to expand main memory capacity, on-chip cache capacity, and memory bandwidth as well as reduce decompression time and metadata size. To evaluate the performance of our proposed system over existing systems, we use execution-driven simulation method by modifying a superscalar microprocessor simulator. Our experimental methodology has higher accuracy than previous trace-driven simulation method. The simulation results show that our proposed system reduces execution time by 4-23% compared with conventional memory system without considering the benefits obtained from main memory expansion. The expansion rates of data and code areas of main memory are 57-120% and 27-36%, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.5
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• pp.1061-1066
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• 2012

A digital memory has been widely used as a device for storing information due to its reliable, fast and relatively simple control circuit. However, the storage of the digital memory will be limited by the inablility to make smaller linewidths. One way to dramatically increase the storeage capability of the memory is to change the type of stored data from digital to analog. The analog memory fabricated in a standard single poly 0.6um CMOS process has been developed. Single cell and adjacent circuit block for programming have been designed and characterized. Applications include low-density non-volatile memory, control of redundancy in SRAM and DRAM memories, ID or security code registers, and image and sound memory.

• Journal of KIISE:Software and Applications
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• v.34 no.8
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• pp.708-720
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• 2007

Memory access errors are frequently occurred in computer programs written in C programming language [1,2]. Accordingly, a number of research works have suggested a wide variety of methods to detect such errors automatically. However, they have one or more of the following problems: inability to detect all memory errors, changing the memory allocation mechanism, and excessive performance overhead. To cope with these problems, in this paper we suggest a new and automated tool to detect dynamic memory access errors in C programs.