• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.43-50
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• 2005

In this paper, quaternary logic gates using Down literal circuit(DLC) has been designed, and then synchronous Quaternary un/down counter using those gates has been proposed The proposed counter consists of T-type quaternary flip flop and 1-of-2 threshold-t MUX, and T-type quaternary flip flop consists of D-type quaternary flip flop and quaternary logic gates(modulo-4 addition gates, Quaternary inverter, identity cell, 1-of-4 MUX). The simulation result of this counter show delay time of 10[ns] and power consumption of 8.48[mW]. Also, assigning the designed counter to MVL(Multiple-valued Logic) circuit, it has advantages of the reduced interconnection and chip area as well as easy expansion of digit.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.4
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• pp.75-81
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• 2013

We presents a novel (2, 2) secret sharing (SS) scheme for all grayscale images. Generally, a secret image is distribute more than two shadow images, which are dealt out among participants. In order to find out secret image, participants print shadow images to transparent papers. Then, a secret image will appear as stacking transparent papers. The secret sharing scheme in this paper distribute secret image into natural grayscale images using multiplexer and data hiding scheme. After then, two participant have two shadow images respectively. The merit of the proposed scheme is that shadow images have small loss in aspect of the quality with steganographic features. Therefore, the proposed secret sharing scheme in this paper is not easily detected by attackers. The experiment result verified that the proposed scheme, obviously outperforms previous SS schemes.

• Korean Journal of Optics and Photonics
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• v.17 no.5
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• pp.430-436
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• 2006

Polarization-independent $Ti:LiNbO_3\;2{\times}2$ optical add/drop multiplexer for the 1550nm wavelength region is fabricated. The device consists of two input waveguides, two polarization beam splitters. two polarization conversion/electrooptic tuning waveguide sections, and two output waveguides. The single mode channel waveguides for both TE and TM polarizations are fabricated on a x-cut $Ti:LiNbO_3$substrate by Ti diffusion. Spectral section is based on phase-matched polarization conversion due to shear strain induced by a thick $SiO_2$ grating overlay film. An applied voltage tunes the device by changing the waveguide birefringence, hence the optical wavelength at which most efficient polarization conversion occurs. Tuning rate of 0.094nm/V with a maximum range of 17nm has been obtained. The nearest side-lobe is about 8.2dB. The FWHM is 3.72nm.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1858-1860
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• 1999

To fabricate superconducting multiplexers with narrow pass band characteristics and reduce the physical size of device, we have designed multiplexer using hair-pin type filters with the center frequency of 13.6 GHz. Multiplexers have been fabricated superconductor(HTS), because It has low surface resistance. The $YBa_2Cu_3O_{7-{\delta}}$(YBCO) films were deposited on MgO substrates$(20{\times}20{\times}0.5mm^3)$ by using pulsed laser deposition and conventional photo-lithographic methods were used to pattern the multiplexer. Epitaxial YBCO films were grown on(100) MgO substrates and showed strongly c_axis orientations observed by X-ray diffraction technique. Superconducting transition temperatures were measured to be about 89K. Simulated results of superconducting multiplexer consisting of hair-pin type filters show the insertion loss of about 1.2dB. The measured frequency response will be compared with the simulated results.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10b
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• pp.619-621
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• 2004

유비쿼터스 컴퓨팅에 대한 연구가 활발하게 전개되고 있는 지금, PC에서뿐만 아니라 언제 어디서나 가능한 모바일 환경에서 다양한 사용자 인터랙션에 중점을 두고 떨러 가지 기하객체들과 이미지, 텍스트 객체 등을 지원함으로써 PDA의 고유의 특성을 이용하고 또 이에 알맞은 PDA환경에서 전문적인 저작도구를 개발하는 것이 필요하다. 따라서 PDA와 같은 제한된 스크린 사이즈와 메모리 공간에서 작은 메모리를 사용하여 얼마나 풍부한 컨텐츠가 저작가능한가 하는 것이 아주 중요하다 본 논문은 PDA환경에서 기하객체와 텍스트, 이미지 등 객체들을 이용하여 MPEG-4 컨텐츠 저작함에 있어서 기존의 저작도구의 기초 위에서 PDA환경의 고유 특성을 고려하여 BIFS 텍스트 생성 모듈, BIFS 인코더 모듈. 멀티플렉서 모듈에 대한 최적화 기법을 연구하며 더 나아가서 PDA환경에 보다 적합하면서도 직접적이고도 시각적인 저작이 가능한 MPEG-4 컨텐츠 저작시스템을 제안하고 그 개발 결과를 보인다.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.699-702
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• 2005

This paper describes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit and decoding circuit. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 DEMUX (demultiplexer) was designed using a 0.35um standard CMOS technology. Proposed circuit is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2002.05a
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• pp.179-182
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• 2002

GA(Genetic Algorithm)는 자연계 진화를 모방한 계산 알고리즘으로서 단순하고 응용이 쉽기 때문에 여러 분야에 전역적 최적해 탐색에 많이 사용되고 있다. 최근에는 하드웨어를 구성하는 방법의 하나로서 사용되어 진화하드웨어라는 분야를 탄생시켰다. 이와 함께 GA의 연산자체를 하드웨어로 구현하는 GA processor(GAP)의 필요성도 증가하고 있다. 특히 진화하드웨어를 소프트웨어상에서 진화 시키는 것이 아닌 GAP에 의해 진화 시키는 것은 독립된 구조의 진정한 EHW 설계에 필수적이 될 것이다. 본 논문에서는 GAP 설계 방법을 제안하고 이를 이용하여 진화하드웨어로 State machine을 구현하고자 한다. State machine의 경우 구조상 피드백이 필요하기 때문에 가산기나 멀티플렉서보다는 훨씬 복잡하고 설계가 까다로운 구조이다. 제안된 방법을 통하여 명시적 설계가 어려운 하드웨어 설계에 GAP를 이용한 하드웨어의 진화에 적용함으로써 그 유용성을 보인다.

• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.54-60
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• 1994

In this paper, the multi-sensor signal processing IC is designed. It consists of an analog multiplexer for selection of multi-sensor signals, active filters for noise rejection and signal amplification, and a sample and hold circuit for interface with digital signal processing. By implementing these circuits with CMOS transistors, integration, low power dissipation and miniaturization of the total signal processing system have been made possible.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1160-1164
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• 1998

In this paper, we propose a new algorithm for computing multiplicative inverses in $GF(2^{m})$ and design an inversion circuit and a division circuit using this algorithm. The algorithm used is based on Fermat's theorem. It takes around m/2 clock cycles. The hardware requirements of the inversion circuit and the division circuit using this algorithm are the same as traditional circuits except for the addition of multiplexers.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.5
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• pp.88-92
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• 2006

Proto Flight Model of Reaction Wheel Assembly Interface Unit(RIU) for STSAT-2 was developed. The RIU of STSAT2 has three major functions for interface between satellite system and RWAs. It has switches for RWA main power, communication Mux. and communication line driver.