• Journal of IKEEE
• /
• v.7 no.2 s.13
• /
• pp.166-171
• /
• 2003

In this paper, we propose a minimal power data path allocation algorithm for low power circuit design. The proposed algorithm minimizes switching activity for input variables in scheduled CDFG. Allocations are further divided into the tasks of register allocation and module allocation. The register allocation algorithm execute that it eliminate spurious switching activity in functional unit and minimize the numbers of multiplexer. Also, resource allocation method selects a sequence of operations for a module such that the switching activity is reduced. Therefore, the algorithm executes to minimize the switching activity of input values, sequence of operations and number of multiplexer. Experimental results using benchmarks show that power is reduction effect from 13% to 17% power consumption, when compared with the Genesis-lp high-level synthesis system.

• Journal of IKEEE
• /
• v.17 no.2
• /
• pp.119-128
• /
• 2013

This paper proposes and implements an core transform architecture, which is one of the major processes in HEVC video compression standard. The proposed core transform architecture is implemented with only adders and shifters instead of area-consuming multipliers. Shifters in the proposed core transform architecture are implemented in wires and multiplexers, which significantly reduces chip area. Also, it can process from $4{\times}4$ to $16{\times}16$ blocks with common hardware by reusing processing elements. Designed core transform architecture in 0.13um technology can process a $16{\times}16$ block with 2-D transform in 130 cycles, and its gate count is 101,015 gates.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.22 no.12
• /
• pp.64-70
• /
• 2008

In case that conventional PRC(Pseudo-Randomized Frequency Carrier) modulation scheme is applied to a three-phase HBML(H-Bridge Multi-Level Inverter), the dominant harmonics spectra appear at twice switching frequency. In this paper, the dominant harmonics spectra spreading effect of the conventional PRC scheme was improved by using three stage MUXs(Multiplexers) and two triangular carriers with fixed frequency which has mutual relation of the twice frequency. To confirm the validity of the improved PRC scheme, the experiment were performed on a 1.5[kw] three-phase HBML based induction motor drives. And, the harmonics spectra of the conventional and improved PRC schemes are compared and discussed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.05a
• /
• pp.76-79
• /
• 2010

Internet of the Web-based Home Securiy, ITS (Intelligent Traffic System), the tourism industry, production field, etc In many fields, using a network camera imaging system has been spotlighted and Accordingly the demand for network cameras is growing rapidly. in order to control it according to the video server complex has a costly problem. In this paper, according to an increasing number of cameras cost and complexity of the video server problems to solve information from video cameras through multi-channel input single-channel multiplex and the fact that switching is handled and Also, the system automatically switches the image data is implemented.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.6
• /
• pp.779-792
• /
• 1993

In a switching node or an ATM multiplexer of the ATM network, a good bandwidth utilization can be achieved by the priority control using the 1-bit(Cell Loss priority) in ATM cell header. In this paper, the mixed mechanism is proposed to make up for shortcomings of existing space priority control mechanisms and to decrease the loss probability of high priority cell and its performance is analyzed about the cell loss probability. To estimate the performance of proposed mixed mechanism, its cell loss probability is compared with those of non-priority mechanism, push-out mechanism and partial buffer sharing mechanism. The cell loss probability is analyzed using a M/D/1/N modeling and a 2-state MMPP/D/1/N modeling and also comparison between two modelings is made. To verify this result of numerical analysis, the computer simulation is performed for each mechanism using the simulation language, SIMSRIPT II.5.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.5 s.335
• /
• pp.15-22
• /
• 2005

This paper proposes an efficient structure which is able to perform self-detection and self-repair for faults in a digital system by imitating the structure of living beings. The self-repair system is composed of artificial cells, which have homogeneous structures in the two-dimension, and spare cells. An artificial cell is composed of a logic block based on multiplexers, and a genome block, which controls the logic block. The cell is designed using DCVSL (differential cascode voltage switch logic) structure to self-detect faults. If a fault occurs in an artificial cell, it is self-detected by the DCVSL. Then the artificial cells which belong to the column are disabled and reconfigured using both neighbour cells and spare cells to be repaired. A self-repairable 2-bit up/down counter has been fabricated using Hynix $0.35{\mu}m$ technology with $1.14{\times}0.99mm^2$ core area and verified through the circuit simulation and chip test.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.4A
• /
• pp.434-439
• /
• 2008

This paper proposes an efficient coarse frequency synchronizer for digital video broadcasting - second generation (DVB-S2). The input signal requirement of acquisition range for coarse frequency estimator in the DVB-S2 is around ${\pm}1.5625Mhz$, which corresponds to 6.25% of the symbol rate at 25Mbaud. At the process of analyzing the robust algorithm among data-aided approaches, we find that the Luise & Reggiannini (L&R) algorithm is the most promising one for coarse frequency estimation with respect to estimation performance and complexity. However, it requires many multipliers and adders to compute output values of correlators. We propose an efficient architecture identifying the serial correlator with the buffer and multiplexers. The proposed coarse frequency synchronizer can reduce the hardware complexity about 92% of the direct implementation. The proposed architecture has been implemented and verified on the Xilinx Virtex II FPGA.

• Journal of IKEEE
• /
• v.10 no.2 s.19
• /
• pp.128-133
• /
• 2006

This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.8
• /
• pp.46-51
• /
• 2002

A new interleaved synchronous mirror delay(SMD) is proposed in order to reduce the circuit size and the power. The conventional interleaved SMD has multiple pairs of forward delay array(FDA) and backward delay away(BDA) in order to reduce the jitter. The proposed interleaved SMD. requires one FDA and one BDA by changing the position of multiplexer. Moreover, the proposed interleaved SMD solves the polarity problem with just one extra inverter. Simulation results show that about 30% power reduction and 40% area reduction are achieved in the proposed interleaved SMD. All circuit simulations and implementations are based on a 0.25um two-metal CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.9B
• /
• pp.1668-1675
• /
• 1999

In this thesis, a narrowband bandpass filter using HTS is proposed for the multiplexer of the satellite communication subsystems. The proposed structure using HTS provides the narrower band and the lower insertion loss characteristics than the conventional parallel-coupled-line bandpass filter. The filter structure using hairpin-line only cause the spurious modes due to the surface waves. But these modes can be lessened by using the hybrid hairpin-line/parallel-coupled-line proposed in this thesis. The narrowband bandpass filters using HTS at the operation frequency of 14.25 GHz are fabricated to have the narrow bandwidth less 1% and the insertion loss less 3dB in comparison with the normal metal microstrip filter with the same three poles. The experimental results show that the filter using HTS has the characteristics of the narrower bandwidth and less insertion loss and can be fabricated with more compact size in comparison with the bandpass filter using normal metal.