• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.3
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• pp.58-69
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• 2003

위성 통신의 수요가 증가하고 있고, 무궁화 위성 등 우리 위성이 발사되면서 위성 탑재체의 국내 개발이 꾸준히 진행되고 있다. 위성 탑재체의 채널 성능은 채널 필터와 입출력 멀티플렉서의 주파수 특성에 의해 크게 좌우된다. 이 글에서는 채널 필터와 멀티플렉서의 구성과 설계에서의 고려 사항에 대해 검토하겠다. 채널 필터를 포함하는 멀티플렉서는 전기적 설계뿐만 아니라 기계적, 열적 설계에서도 까다로운 사양을 요구하고 있다. 채널필터는 소형 경량화의 요구에 따라 주로 이중 모드(dual mode) 필터로 설계되고 있고, 최근에는 HTS 필터에 의한 설계도 시도되고 있다. 입력 멀티플렉서는 채널 사이의 간섭을 방지하기 위해 써큘레이터를 이용하여 구성하고, 출력 멀티플렉서는 손실을 최소화하기 위하여 매니폴드(manifold)를 이용하여 채널필터를 결합한다. 이 글은 Kunes와 Kudsia의 논문을 주로 참조하였다.

• Journal of the Korea Society of Computer and Information
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• v.5 no.4
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• pp.82-89
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• 2000

This study analyzes the cell loss probability of an ATM multiplexer with real time and non-real time bursty traffics. It is assumed that an ATM multiplexer with loss priority control for the analysis. The loss priority control uses the CLP Reld of cell header. For easy analysis and less computation. the multiplexed traffic of the ATM multiplexer was modeled by the MMDP. The ATM multiplexer is simulated by the MMDP/MMDP/l/K queueing system. From the above results, The connection admission of an ATM multiplexer with loss priority control is determined by the cell loss probability with low priority as well as the size of threshold buffer. Therefore, to increase the statistical multiplexing gain it will be good to utilize the loss priority control in order.

• The Journal of the Convergence on Culture Technology
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• v.6 no.4
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• pp.819-824
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• 2020

In this paper, we propose a new multiplexer using quantum dot cellular automata (QCA), a next-generation digital circuit design technology. A multiplexer among digital circuits is a circuit that selects one of the input signals and transfers the selected input to one line. Since it is used in many circuits such as D-flip-flops, resistors, and RAM cells, research has been conducted in various ways to date. However, the previously proposed planar structure multiplexer does not consider connectivity, and therefore, when designing a large circuit, it uses an area inefficiently. There was also a multiplexer proposed as a multi-layer structure, but it does not improve the area due to not considering the interaction between cells. Therefore, in this paper, we propose a new multiplexer that improves 38% area reduction, 17% cost reduction, and connectivity using a cell-to-cell interaction and multi-layer structure.

• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.135-140
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• 2008

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.2
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• pp.147-154
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• 1990

A 4:1 Time Division Multiplexer(MUX) had been designed in using GaAs Source Coupled FET Logic(SCFL), Designed Multiplexer uses a time division frequency divider and two stage of singnal combining 2:1 multiplexer. The performance of the multiplexer is verified by PSPICE simulation. Designed circuit operates up to 12.5Gbit/s with a power dissipation of 192mW. These performance are more advanced than other reported multiplexer in the speed and power dissipation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.121-126
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• 2007

This paper describes a 9.09 Gb/s CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with Samsung $0.35{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the post layout simulation. The demultiplexer is achieved the maximum data rate of 9.09 Gb/s and the average power consumption of 69.93 mW. This circuit is expected to operate at higher speed than 9.09 Gb/s in the deep-submicron process of the high operating frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.7
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• pp.706-712
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• 2004

This paper presents the design technique of output multiplexer(OMUX) for the Ka-band satellite transponder. Output multiplexer consists of low-pass filter(LPF), channel filter and manifold. Channel filters adopt dual-mode technique in design for mass and volume reduction and frequency response of channel filters is 4-pole elliptic response for high frequency selectivity. w-pass filters are designed to be of 13th order corrugated type for high rejection characteristic over reception band of satellite transponder. After initial design of channel filters and manifold, we optimized only a few design parameters for fast and easy optimization instead of optimizing all the design parameter. Measured results of a realized output umltiplexer for Ka-band satellite transponder show good agreement with the computed ones.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.2
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• pp.99-107
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• 2003

This paper proposes a design for testability (DFT) and testability analysis method for register-transfer level (RTL) circuits. The proposed method executes testability analysis - controllability and observability - on the RTL circuit and determines the insertion points to enhance the testability. Then with the associated priority based on the testability, we insert only a few of the test multiplexers resulting in minimized area overhead. Experimental results shows a higher fault coverage and a shorter test generation time than the scan method. Also, the proposed method takes a shorter test application time required.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.1A
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• pp.47-53
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• 2003

This paper describes the design of a 155 Mb/s multiplexer-demultiplexer chip. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s serial data output, and is to deinterleave a serial input bit stream of 155 Mb/s into the parallel output of 51 Mb/s The input and output of the device are TTL compatible at the low-speed end, but 100K ECL compatible at the high-speed end The device has been fabricated with a 0.7${\mu}m$ BiCMOS gate array The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 470 ps at the high-speed end. And power dissipation is evaluated under 2.0W.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.13-19
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• 2020

In this paper, we propose a multiplexer based scheme that performs modular AB² multiplication using redundant basis over finite field. Then we propose an efficient multiplexer based semi-systolic AB² multiplier using proposed scheme. We derive a method that allows the multiplexers to perform the operations in the cell of the modular AB² multiplier. The cell of the multiplier is implemented using multiplexers to reduce cell latency. As compared to the existing related structures, the proposed AB² multiplier saves about 80.9%, 61.8%, 61.8%, and 9.5% AT complexity of the multipliers of Liu et al., Lee et al., Ting et al., and Kim-Kim, respectively. Therefore, the proposed multiplier is well suited for VLSI implementation and can be easily applied to various applications.