• IT SoC Magazine
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• s.19
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• pp.49-49
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• 2007

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.62-68
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• 2007

H.264 video compression in digital multimedia broadcasting (DMB) shows significantly high compression ratio over conventional algorithms, while its required hardware cost and power consumption are also $3{\sim}5$ times larger. Consequently, low-hardware-cost and low-power H.264 decoder SoC is essential for commercial digital multimedia broadcasting terminals. This paper describes low-power design and implementation of core blocks in H.264 decoder SoC.

• Korea Multimedia Society
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• v.16 no.1
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• pp.1-8
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• 2012

• Smart Media Journal
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• v.1 no.1
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• pp.27-35
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• 2012

In this paper, the performance analysis for multimedia video codec(MPEG-4, H.264) on on-chip network communication architecture is presented. The On-Chip Network (OCN) is the new communication architecture of multimedia SoC design that overcomes the limits of On-Chip Bus architecture by providing higher data traffic bandwidth, reusability and higher scalability. We compared the performance of MPEG-4, H.264 decoder based on-chip network and AMBA on-chip bus. Experimental results show that the performance of MPEG-4, H.264 based on on-chip network is improved over 33~56% compared to the design based on AMBA on-chip bus.

• Annual Conference of KIPS
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• 2009.04a
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• pp.856-858
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• 2009

최근 휴대폰, PMP 와 같은 모바일 장치를 개발하는 데에 그 성능과 저전력화 SoC 기술을 적용하고 있다. 또한 화상통화와 같은 영상 및 음성 멀티미디어 서비스가 확장되고 있다. 그러나 현재 모바일 SoC 기술에서 멀티미디어 서비스의 실시간 요구사항을 고려한 네트워크 프로토콜 설계에 대한 연구가 부족하다. 이에 본 논문에서는 실시간성 모바일 SoC 에서 실시간성을 제공하는 네트워크 프로토콜 스택을 설계하는 기법을 제안하고자 한다. 그리고 제안한 기법이 구현된 실시간 네트워킹 SoC 플랫폼의 성능을 실험하였으며, 그 결과 기존의 기법보다 더 좋음을 확인하였다.

• The Journal of the Korea Contents Association
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• v.7 no.11
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• pp.84-93
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• 2007

This paper presents a methodology that accelerates estimating the system-level power consumption for on-chip bus of SoC platforms. The proposed power modeling can estimate the power consumption according to the change of a target SoC system. The proposed model comprises two parts: the one is power estimation of bus logics reflecting the architecture of the bus such as the number of bus layers, the other is to estimate the power consumed by the bus lines during data transmission. We designed the target multimedia SoC system, MPEG encoder as an example and evaluated power consumption using this model. The simulation result shows that the accuracy of the proposed model is over 92%. Thus, the proposed power model can be used to design of a high-performance/low-power multimedia SoC.

• IT SoC Magazine
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• s.18
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• pp.10-24
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• 2007

본 코너에서는‘07년 1월호 핫이슈에서 다룬‘IT부품 2007-2012 기술로드맵’을 토대로 홀수 월에 각 분야별로 시장/기술 동향, 표준화/정책 동향 및 기술로드맵을 상세히 다루고 있습니다. 독자 여러분께서도 본 내용과 관련하여 중장기적으로 반드시 포함해야 할 중요한 연구개발 테마가 있으면 IITA의‘IT부품/융합기술 전문위원실’에 알려주시기 바랍니다. 준비한 기술로드맵을 참고하여 차기 기술개발 테마를 발굴해 나갈 예정입니다. 이번호에서는‘통방/멀티미디어 컨버전스 부품 기술로드맵에 대해서 다룹니다.

• Korea Multimedia Society
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• v.16 no.3
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• pp.1-7
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• 2012

• The KIPS Transactions:PartD
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• v.8D no.1
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• pp.44-53
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• 2001

It is very important how users query MM data and how the query results are presented in MMDB systems. Also, the query results are represented as the generalized form so as to be used in various applications. In this paper, we propose a generalized method for querying and presenting MM data by extending query language based on presentation elements of SMIUSMIL is W3C recommendation for synchronized MM presentation). Our system provides the query results for users as SMIL format in order to be used for various applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.397-400
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• 2009

This paper describes ASIC design of Multimedia application SoC platform based RISC processor with BTB(Branch Target Buffer). For performance enhancement of platform, we use a simple branch prediction scheme, BTB structure, that stores a target address for branch instruction to remove pipeline harzard. Also, the platform includes a number of peripheral such as VGA controller, AC97 controller, UART controller, SRAM interface and Debug interface. The platform is designed and verified on a Xilinx VERTEX-4 FPGA using a number of test programs for functional tests and timing constraints. Finally, the platform is implemented into a single ASIC chip which can be operated at 100MHz clock frequency using the Chartered 0.18um process. As a result of performance estimation, the proposed platform shows about 5~9% performance improvement in comparison with the previous SoC Platform.