• Journal of Korea Multimedia Society
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• v.15 no.10
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• pp.1247-1256
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• 2012

There are many filter based image processing algorithms and they usually require a huge amount of computations and memory accesses making it hard to attain a real-time performance, expecially in embedded applications. In this paper, we propose a pipelined hardware structure of the filter based face detection algorithm to show that the real time performance can be achieved by hardware design. In our design, the whole computation is divided into three pipeline stages: resizing the image (Resize), Transforming the image (ICT), and finding candidate area (Find Candidate). Each stage is optimized by considering the parallelism of the computation to reduce the number of cycles and utilizing the line memory to minimize the memory accesses. The resulting hardware uses 507 KB internal SRAM and occupies 9,039 LUTs when synthesized and configured on Xilinx Virtex5LX330 FPGA. It can operate at maximum 165MHz clock, giving the performance of 108 frame/sec, while detecting up to 20 faces.

• Journal of Korea Multimedia Society
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• v.11 no.11
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• pp.1592-1600
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• 2008

This study is to help creative idea generation based on the theory of the 'reconstruction of character shape image elements', and aims to extrusion of creative and diverse shapes with combination of image elements upon computing creative image generation. In order to suggest the design generation methodology for the maximization of idea generation ability and to overcome restriction of thinking out of existing idea generation methodology, it has suggested the CGS(Character Generation System) that is a creative idea generation methodology identified and complemented the problem of the existing computerized idea generation(PDS with Proportion) method out of the preceded studies on the creative idea generation methodologies. this study is expected to have effectives as one method for idea generation or creative image generation assistance during the 3D character development process, and to serve as an assistance to overcome the restriction of the character shape image generation through diverse idea generations.

• Journal of Korea Multimedia Society
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• v.14 no.3
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• pp.462-470
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• 2011

Retargetability is typically achieved by providing target machine information, ADL, as input. The ADL are used to specify processor and memory architectures and generate software toolkit including compiler, simulator, etc. Simulator are critical components of the exploration and software design toolkit for the system designer. They can be used to perform diverse tasks such as verifying the functionality and/or timing behavior of the system, and generating quantitative measurements(e.g., power energy consumption) which can be used to aid the design process. In this paper, we generate the energy consumption estimation simulator through ADL. For this goal, firstly, we describes the energy consumption estimation and monitoring informations on the ADL based on EXPRESSION. Secondly, we generate the energy estimation and monitoring simulation library and then constructs the simulator, RenergySim. Lastly, we represent the energy estimations results for MIPS R4000 ADL description. From this subjects, we contribute to the efficient architecture developments and prompt SDK generation through programmable experiments in the field of mobile software development.

• Journal of Korea Multimedia Society
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• v.14 no.3
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• pp.368-377
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• 2011

This paper explains the hardware structure of SURF(Speeded Up Robust Feature) based feature point extractor and its FPGA verification result. SURF algorithm produces novel scale- and rotation-invariant feature point and descriptor which can be used for object recognition, creation of panorama image, 3D Image restoration. But the feature point extraction processing takes approximately 7,200msec for VGA-resolution in embedded environment using ARM11(667Mhz) processor and 128Mbytes DDR memory, hence its real-time operation is not guaranteed. We analyzed integral image memory access pattern which is a key component of SURF algorithm to reduce memory access and memory usage to operate in c real-time. We assure feature extraction that using a Vertex-5 FPGA gives 60frame/sec of VGA image at 100Mhz.

• Journal of Korea Multimedia Society
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• v.3 no.6
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• pp.674-684
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• 2000

One key obstacle which has been identified in achieving parallel processing is to communicate effectively between processors during execution. One approach to achieving an optimal delay time is to use expander graph. The networks and algorithms which are based on expander graphs are successfully exploited to yield fast parallel algorithms and efficient design. The AKS sorting algorithm in time O(logN) which is an important result is based on the use of expanders. The expander graph also can be applied to construct a concentrator and a superconcentrator. Since Margulis found a way to construct an explicit linear expander graph, several expander graphs have been developed. But the proof of existence of such graphs is in fact provided by a nonconstructive argument. We investigate the expander network on the hypercube network. We prove the expansion of a sin81e stage hypercube network and extend this from a single stage to multistage networks. The results in this paper provide a theoretical analysis of expansion in the hypercube network.

• Journal of Korea Multimedia Society
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• v.15 no.7
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• pp.870-878
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• 2012

Recently, very rapid development of computer and sensor technologies induces various kinds of user interface (UI) technologies based on user experience (UX). In this study, we investigate and develop a smart touch projector system technology on the basis of IR sensor and image processing. In the proposed system, a user can control computer by understanding the control events based on gesture of IR pen as an input device. In the IR image, we extract the movement (or gesture) of the devised pen and track it for recognizing gesture pattern. Also, to correct the error between the coordinate of input image sensor and display device (projector), we propose a coordinate correction algorithm to improve the accuracy of operation. Through this system technology as the next generation human-computer interaction, we can control the events of the equipped computer on the projected image screen without manipulating the computer directly.

• Journal of Korea Multimedia Society
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• v.11 no.7
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• pp.928-939
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• 2008

The grid database management system is used for large data processing, high availability and data integration by grid environment. It has a replica for processing performance and high availability in each node. The grid database has a problem of inconsistency, when the update is occurred with a coincidently frequent. To solve this problem, in this paper proposed a version management method for consistency in the grid database. Proposed version manager manages a version of each replica. The version manager keeps a consistency of update operation when is occurred at each node by using a pending queue and waiting queue. Also the node keeps a consistency using a priority queue. So, proposed method has stable and fast update propagation. The proposed method shows stable and faster update propagation than traditional method by performance evaluation.

• The Journal of the Acoustical Society of Korea
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• v.23 no.8
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• pp.554-561
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• 2004

As the technologies of semiconductor and multimedia communication have been improved. the high-quality video and the multi-channel audio have been highlighted. MPEG Audio Layer 3 decoder has been implemented as a Processor using a standard. Since the synthesis filter of MPEG-1 Audio Layer 3 decoder requires the most outstanding operation in the entire decoder. the synthesis filter that can reduce the amount of operation is needed for the design of the high-speed processor. Therefore, in this paper, the synthesis filter. the most important part of MPEG Audio, is materialized in FPGA using the method of DAULT (distributed arithemetic look-up table). For the design of high-speed synthesis filter, the DAULT method is used instead of a multiplier and a Pipeline structure is used. The Performance improvement by 30% is obtained by additionally making the result of multiplication of data with cosine function into the table. All hardware design of this Paper are described using VHDL (VHIC Hardware Description Language) Active-HDL 6.1 of ALDEC is used for VHDL simulation and Synplify Pro 7.2V is used for Model-sim and synthesis. The corresponding library is materialized by XC4013E and XC4020EX. XC4052XL of XILINX and XACT M1.4 is used for P&R tool. The materialized processor operates from 20MHz to 70MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10B
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• pp.939-945
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• 2008

Tn this paper we described the process and the results of an implementation of Internet terminal using G.729.1 wideband speech codec for next generation network. For this purpose firstly we chose a high performance RISC application processor having DSP features for speech codec processing and enhanced Multimedia Accelerator(eMMA) function for video codec. In the implementation of this terminal, we used G.729.1 codec recently standardized in ITU-T which is a new scalable speech and audio codec that extends 0.729 speech coding standard. To adopt G.729.1 codec to this terminal we transformed most of the fixed point C codes which require more complexity into assembly codes so as to minimize processing time in the processor. As a result of this work we reduced the execution time of the original C codes about 80% and operated in real time on the terminal. For video we used H.263/MPEG-4 codec which is supported by the eMMA with hardware in the processor. In the SIP call processing test connected to real network we obtained under looms end-to-end delay and 3.8 MOS value measured with PESQ instrument. Besides this terminal operated well with commercial terminals.

• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.32-39
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• 2012

In this paper, the implementation of location based services (LBS) using S-DMB (satellite-digital multimedia broadcasting) system was proposed. In S-DMB System, the frequency of transmitted signal is about 2 GHz which has a characteristics of strong straightness but weak diffraction so that there are many shade areas such as indoors and underground spaces. Therefore the signal transmitted from the satellite should be retransmitted by the earth repeaters called as gap filler. Because each gap filler has its own identification value, the gap filler ID introduces the area in which the gap filler was installed. Generally, the 51st data symbols of S-DMB pilot signal transmitted from the satellite are padded by dummy value and gap filler ID is embedded in this pilot symbol by the gap filler when S-DMB signals are retransmitted by gap fillers. So using gap filler ID of S-DMB system, LBS such as region registration, distance and time to destination, alarm of local area information could be implemented. In the experiment to prove the performance of the proposed LBS system using the gap filler ID of the S-DMB system, the firmware of S-DMB chip composing of RF and baseband parts was lightly modified so that application processor was able to manipulate the gap filler ID and the its related regional information.