• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.431-441
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• 2003

This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

• 한국정보교육학회:학술대회논문집
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• 2021.08a
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• pp.25-30
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• 2021

With the introduction of AI education in the 2022 Revised Curriculum emphasizing the need for data related education, it is necessary to improve students' data based problem solving skills. This study seeks to study SW education methods to improve students' data based problem solving skills in accordance with these needs. Based on the ADDIE model, the demand analysis survey was conducted on teachers to analyze their needs. Based on the results of the demand analysis, we designed education programs under the theme of data based problem solving skills using microbit. In this study, we raise the importance of data based problem solving and the need for its capabilities. Subsequent studies need to reveal how data based problem solving SW education will demonstrate significant effects on problem solving skills.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1939-1947
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• 2000

본 논문에서는 명령어의 효율적인 페치를 위해 분기 타겟 주소 전체를 사용하지 않고 캐쉬 메모리(cache memory) 내의 적은 비트 수로 인덱싱 하여 한 클럭 사이클 안에 최대 4개의 명령어를 다음 파이프라인으로 보내줄 수 있는 방법을 제시한다. 본 프리페치 유닛은 크게 나누어 3개의 영역으로 나눌 수 있는데, 분기에 관련하여 미리 부분적으로 명령어를 디코드 하는 프리디코드(predecode) 블록, 타겟 주소(NTA : Next Target Address) 테이블 영역을 추가시킨 명령어 캐쉬(instruction cache) 블록, 전체 유닛을 제어하고 가상 주소를 관리하는 프리페치(prefetch) 블록으로 나누어진다. 사용된 명령어들은 SPARC(Scalable Processor ARChitecture) V9에 기준 하였고 구현은 Verilog-HDL(Hardwave Description Language)을 사용하여 기능 수준으로 기술되고 검증되었다. 구현된 프리페치 유닛은 명령어 흐름에 분기가 존재하더라도 단일 사이클 안에 4개까지의 명령어들을 정확한 예측 하에 다음 파이프라인으로 보내줄 수 있다. 또한 NTA를 사용한 방법은 같은 수의 레지스터 비트를 사용하였을 때 BTB(Branch Target Buffer)를 사용하는 방법과 비교하여 2배정도 많은 개수의 분기 명령 주소를 저장할 수 있는 장점이 있다.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.6
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• pp.525-535
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• 2004

In this paper, a two-phase DZRCD(Dual Zero Vector Modes RCD) technique is proposed to develope the problem of a conventional two-phase RCD-PWM (Random Centered Distribution PWM) which gives the power spectra of narrow band range in the high modulation index (M). In the proposed DZRCD technique, the zero vector $V_0$ is selected as $V_0$(111) for M$\geqq$0.8. Also, $V_0$ is selected as $V_0$(000) for the modulation indices < 0.8. For the unplementation of the proposed method, a 16-bit micro-controller Cl67 was used and the experiments were conducted with the 1.5kw induction motor under no load condition. The experimental results show that the voltage / current spectra is spread to a wide band range, and the switching noise of motor is reduced by the proposed method compared to the conventional random operation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.649-652
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• 2013

LEON3 is a 32-bit synthesisable processor based on the SPARC V8. It can be connected to AMBA 2.0 bus and has a 7-stage pipeline, IEEE-754 FPU and 256[KB] cache. It can be easily implemented using FPGA and used for a SoC design. DSU which comes with LEON3 can be used to control and monitor the operation of LEON3. And DSU makes it easy to set a debugging environment for the development of both hardware and software for an embedded systems based on LEON3. This paper presents the summary of the development of LEON3 monitoring software.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3111-3113
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• 1999

임베디드 메모리로직에 적용되는 매크로셀을 지니고 전류형태의 저장방법을 적용한 캐시를 통한 임베디드 메모리칩의 설계의 일환으로 0.25마이크로 공정으로 설계되었으며 멀티미디어 칩에 사용되는 메모리 코아는 캐시를 지니고 있음으로 칩의 밴드위스를 높이고 칩의 어드레스 억세스시간(10nS)을 빠르게 할 수 있었으며 이를 위한 내부공급전압은 2.0V이다. 본 논문의 아키텍쳐에서는 기존 메모리 소자의 전송형태를 전류형 전송수단을 이용하여 매크로 셀의 데이터를 캐시에 저장하고, 이를 전류형태의 메인 데이터증폭회로를 통하여 전송하게된다. 이를 이루기 위한 칩의 아키텍척로 비트라인과 캐시의 연결회로를 추가한 구조를 제안하였다.

• Journal of KIISE
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• v.43 no.1
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• pp.34-39
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• 2016

JavaScript is widely used in web pages with HTML. Many JavaScript engines adopt Just-in-time compilers to accelerate the execution of JavaScript programs. Recently, many newly introduced devices are adopting 64-bit CPUs instead of 32-bit and Just-in-time compilers for 64-bit CPU are slowly being introduced in JavaScript engines. However, there are many inefficiencies in the currently available Just-in-time compilers for 64-bit devices. Especially, the size of code is significantly increased compared to 32-bit devices, mainly due to 64-bit wide addresses in 64-bit devices. In this paper, we are going to address the inefficiencies introduced by 64-bit wide addresses and values in the Just-in-time compiler for the V8 JavaScript engine and propose more efficient ways of generating constant values and addresses to reduce the size of code. We implemented the proposed optimization in the V8 JavaScript engine and measured the size of code as well as performance improvements with Octane and SunSpider benchmarks. We observed a 3.6% performance gain and 0.7% code size reduction in Octane and a 0.32% performance gain and 2.8% code size reduction in SunSpider.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.35 no.2
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• pp.129-135
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• 1999

The telemetry system for the current speed and direction, the underwater ambient noise and the distribution ecology of fishes was constructed by the author and his collaborator in order to product and manage effectively in shallow sea culture and setnets fisheries, and then the experiments for the telemetry system carried out at set net fishing ground located Nungpobay in Kojedo from October 1996 to June 1997. As this results, the techniques suggested in the telemetry system gave full display its function even though far away 1.5 km from transmitting part, but with the suggested telemetry system could not be ascertained relationship between physical environment and distribution ecology of fishes.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.28 no.3
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• pp.253-262
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• 1995

To develop a device for measuring fish freshness which could be move accurate and reliable than used freshness measuring systems. A new device based on digital circuit was designed using a microcomputer. The device was composed of a sensor part, 8096 microprocessor and a segment display. The effectiveness of device has been evaluated by the coefficient of correlation among the measured freshness stores such as electrical Q-value, K-value and amount of volatile basic nitrogen (VBN) of plaice, Paralichthys Olivaceus, during storage at $-3^{\circ}C,\;0^{\circ}C,\;5^{\circ}C,\;10^{\circ}C,\;and\;25^{\circ}C$. Q-values measured by a new device were more closely correlated with K-value (r=-0.978-\;-0.962,\;p<0.05) and VBN (r=-0.888-\;-0.988,\;p<0.05) in case of plaice meat. If more data would achieve using various fishes, this new designed device could be a valuable kit in fish market by its compact portability.