• Title/Summary/Keyword: 리드-솔로몬 부호

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A Performance Analysis of FEC Coding Method in Rayleigh Satellite Return Link Channel (레일리 위성 리턴링크 채널에서 FEC 부호 방식 성능분석)

  • Lee Seong Ro;Cho Sung Eui;Oh Deock gil
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.12C
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    • pp.1633-1641
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    • 2004
  • In satellite digital broadcasting and satellite internet, severe burst errors occur in the high-speed return channel from the satellite to mobiles. In this paper, we analyze the performance of the forward error correction (FEC) coding method in the Rayleigh fading return channel. We first investigate the channel model of Loo, LutB, Vucetic and Corazza. We then compare the performance of the convolutional, Reed-Solomon (RS), convolution-RS concatenation, and Turbo codes in rayleigh fading channel.

Complexity Analysis of a VHDL Implementation of the Bit-Serial Reed-Solomon Encoder (VHDL로 구현된 직렬승산 리드솔로몬 부호화기의 복잡도 분석)

  • Back Seung hun;Song Iick ho;Bae Jin soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.3C
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    • pp.64-68
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    • 2005
  • Reed-Solomon code is one of the most versatile channel codes. The encoder can be implemented with two famous structures: ordinary and bit-serial. The ordinary encoder is generally known to be complex and fast, while the bit-serial encoder is simple and not so fast. However, it may not be true for a longer codeword length at least in VHDL implementation. In this letter, it is shown that, when the encoder is implemented with VHDL, the number of logic gates of the bit-serial encoder might be larger than that of the ordinary encoder if the dual basis conversion table has to be used. It is also shown that the encoding speeds of the two VHDL implemented encoders are exactly same.

Tradeoffs in frequency-hopped multiple-access communications with reed-solomon code and MFSK in rayleigh fading channel (레일리 페이딩 채널에서 리드-솔로몬 부호와 MFSK를 사용하는 주파수 도약 다중 접속 통신의 Tradeoff)

  • 김상우;김승호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.23 no.9A
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    • pp.2173-2183
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    • 1998
  • We consider a frequency-hopped multiple-access communication system that employs reed-solomon code over GF(Q) and M-ary FSK signaling ($M{\leq}Q$) in rayleigh fading channel. We investigate the tradeoff among the modulation symbol size (M), the number of frequency slots, and the code rate in maximizing the average number of successfully transmitted information bits per unit time and unit bandwidth (called normalized throughput). We find that it is desirabel to use a large M in noise-limited environment. In interference-limited environment, it is more improtant to prevent errors (hits) by increasing the number of frequency slots than to correct them with formward error correction techniques or to reduce the error rate by increasing M.

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Design of a RS(23,17) Reed-Solomon Decoder (RS(23,17) 리드-솔로몬 복호기 설계)

  • Kang, Sung-Jin
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.12
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    • pp.2286-2292
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    • 2008
  • In this paper, we design a RS(23,17) decoder for MB-OFDM(Multiband-Orthogonal Frequency Division Multiplexing) system, in which Modified Euclidean(ME) algorithm is adopted for key equation solver block. The proposed decoder has been optimized for MB-OFDM system so that it has less latency and hardware complexity. Additionally, we have implemented the proposed decoder using Verilog HDL and synthesized with Samsung 65nm library. From synthesis results, it can operate at clock frequency of 250MHz, and gate count is 20,710.

High-Performance Variable-Length Reed-Solomon Decoder Architecture for Gigabit WPAN Applications (기가비트 WPAN용 고성능 가변길이 리드-솔로몬 복호기 구조)

  • Choi, Chang-Seok;Lee, Han-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.1
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    • pp.25-34
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    • 2012
  • This paper presents a universal architecture for variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS(255,239) code but various shortened RS codes. Moreover, variable-length architecture provides variable low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-$nm$ CMOS standard cell technology, the proposed RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-$Gbps$ data rate at clock frequency 300 $MHz$.

Performance Analysis of Hybrid Automatic Repeat Request Systems Using Shortened Reed-Solomon Codes over Rayleigh Fading Channel (레일레이 페이딩 채널에서 단축된 리드-솔로몬 부호를 사용한 하이브리드 제전송요구방식의 성능분석)

  • 이정운;양경철
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.3
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    • pp.731-736
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    • 1996
  • In this paper, we propose a modified Type-II HARQ system having adaptive power to channel and analyze its performance in terms of throughput and reliability. Its performance is also compared with Typd-I and Type-II HARQ ystems and is verified using computer simulations over AWGN and frequenyc-nonselective, slowly Rayleigh fading channels.

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Adaptive Decoding Scheme of Concatenated Codes for Frequency-Hopped Spread-Spectrum Communications with a Pulse-Burst Jamming (펄스형 Jamming 신호가 존재하는 주파수 도약 대역확산 통신환경에서 쇄상부호 시스템의 적응 복호화 방식)

  • 김정곤;김성대;김형명
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.7
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    • pp.1234-1243
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    • 1994
  • We propose an adaptive decoding scheme for a concatenated codes with frequency-hopped spread-spectrum communication system in the presence of a pulse-burst jammer and its performance is analyzed. Concatenated coding system employing binary inner code and Reed-Solomon outer code is investigated and the use of side information is allowed to decode both erasures and errors. Our scheme makes the decoder adapts to the level of jamming by switching between two decoding modes such that the overall block error probability can be reduced. It is shown that the proposed decoding scheme yields a significant performance improvement over a conventional decoding scheme.

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Design of Error Correction Encoder for High-Speed PLC Systems (초고속 전력선 통신을 위한 오류정정 부호화기 설계)

  • Choi, Sung-Soo;Park, Hae-Soo;Lee, Jae-Jo;Lee, Won-Tae;Kim, Kwan-Ho
    • Proceedings of the KIEE Conference
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    • 2003.07d
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    • pp.2702-2704
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    • 2003
  • 본 논문은 전력선통신시스템 (Power Line Communications)을 위한 초고속 오류정정 부호화기 회로에 관한 설계방법론과 회로의 동작속도, 회로복잡성과 레이턴시에 직접적으로 기여하는 핵심 GF (Galois Field) 연산기들의 역할 및 이들의 설계결과에 관해 설명한다. 특히, 이러한 설계방법에 충실한 오류정정 부호화기회로는 입출력 병렬구조의 세미-시스톨릭 (Semi-systolic) 아키텍처를 갖는 고속의 내부 핵심 GF 연산기회로들을 채택함으로써 고속 연산을 가능토록 한다. 최적화된 GF곱셈연산기를 기반으로 설계되어진 리드-솔로몬 (Reed-Solomon) 오류정정 부호화기는 전력선 채널상에서 데이터를 전송 시 발생되는 연집오류들을 효과적으로 복원하도록 하는 대표적인 부호화기로 이미 존재하는 다른 회로들에 비해 동작속도, 회로의 복잡성, 및 레이턴시 측면에서 그 성능이 월등히 뛰어나므로, 실제 초고속 전력선 통신시스템의 설계 및 구현 시 효과적으로 이용될 수 있다.

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