• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.380-381
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• 2011

본 논문에서는 PFC 부스트 컨버터의 역률 및 고조파 왜율 개선을 위한 전류 제어기 이득 조정 기법을 제안한다. PFC단은 입력 전압의 변화에 따라 인덕터 전류의 크기가 달라져 부스트 인덕터의 인덕턴스가 변화하게 되어 전류 루프의 주파수 특성이 변화하게 된다. 이러한 현상으로 인한 전류 루프의 이득 변화를 분석하였다. 이를 기반으로 입력 전압에 따라 전류 제어기의 이득을 조정해 줌으로써, 충분한 위상마진을 확보함과 동시에 PF와 THD 성능을 개선한다. TI사의 TMS320F28027 MCU를 이용한 실험을 통해 제안된 기법의 유용성을 검증한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.68-74
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• 2010

A sub-${\mu}$W CMOS Wien-Bridge oscillator for ultra low power (ULP) radio applications is presented. The Wien-Bridge oscillator is based on an non-inverting opamp amplifier with a closed-loop gain $1+R_2/R_1$ as a means of providing necessary loop gain. An additional RC network provides appropriate phase shift for satisfying the Barkhausen oscillation condition at the given frequency of 1/($2{\pi}RC$). In this design, we propose a novel loop gain control method based on a variable capacitor network instead of a rather conventional variable resistor network. Implemented in $0.18{\mu}m$ CMOS, the oscillator consumes only 560 nA at the oscillation frequency of 22 kHz.

• Journal of the Korean Institute of Intelligent Systems
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• v.5 no.3
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• pp.64-72
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• 1995

This paper proposes how to tune the gains of PI controllers in case of gain change in a process control system. Controllers of PI type have been used in industry and the gains of the controllers have been tuned by expert engineers. It, therefore, takes much time and efforts to tune the controllers. It is more difficult to find gains of multi-loop processes. The tuning method of a fuzzy tuner in this paper is developed based on the assumptions that the PI controllers are of analog type and are tuned off-line, and that the characteristic values must be supplied for the tuner. A Tuner using Fuzzy Logic(FLT1 is capable of showing presentlpast states of a process control system and finding gains of PI controllers. The verfication of the FLT is shown by various experiments.

• The KIPS Transactions:PartC
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• v.11C no.6 s.95
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• pp.835-842
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• 2004

In this paper, we have analyzed the MC-DS/CDMA system with input signal synchronized completely through adjustment of the gain in the PLL loop, by using the hybrid SC/MRC-(2/3) technique, which is said to one of the optimal diversity techniques under the multi-path fading environment, assuming that phase error is defined to the phase difference between the received signal from the multi-path and the reference signal in the PLL of the receiver. Also, assuming that the regarded radio channel model for the mobile communication is subject to the Nakagami-m fading channel, we have developed the expressions and performed the simulation under the consideration of various factor, in the MC/DS-CDMA system with the hybrid SC.MRC-(2/3) diversity method, such as the Nakagami fading index(m), $the\;number\;of\;paths\;(L_p),$ the number of hybrid SC.MRC-(2/3) $diversity\;branches\;(L,\;L_c),$ the number of users (K), the number of subcarriers (U), and the gain in the PLL loop. As a result of the simulation, it has been confirmed that the performance improvement of the system can be achieved by adjusting properly the PLL loop in order for the MC/DS-CDMA system with the hybrid SC/MRC-(2/3) diversity method to receive a fully synchronized signal. And the value of the gain in the PLL loop should exceed 7dB in order for the system to receive the signal with prefect synchronization, even though there might be a slight difference according to the values of the fading index and the spread processing gain of the subcarrier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.9C
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• pp.871-878
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• 2002

The cartesian loop chip which is one of key devices in narrow-band Walky-Talky transmitter using RZ-SSB modulation method was designed and implemented with 0.35 ㎛ CMOS technology. The reduced size and low cost of transmitter were available by the use of direct-conversion and cartesian loop chip, which improved the power efficiency and linearity of transmitter. In addition, low power operation was possible through CMOS technology. The performance test results of transmitter showed -23㏈c improvement of IMD and -30㏈c below suppression of SSB characteristic in the operation of cartesian loop chip (closed-loop). At that time, the transmitting power was about 37㏈m (5W). The main parameters to improve the transmitting characteristic and to compensate the distortion in feed back loop such as DC-offset, loop gain and phase value are interfaced with notebook PC to be controlled with S/W.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12C
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• pp.1029-1034
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• 2010

For All Digital QPSK receivers, a phase recovery scheme is required to fix the arbitrarily rotated I/Q quadrature signals due to the transmission path and clock mismatch between the transmitter and the receiver. The conventional Costas phase recovery loop scheme requires a separate AGC(Automatic Gain Control) to obtain the performance independent of input signal power. This paper proposes a simple scheme which separates the phase and amplitude of the input signal via CORDIC algorithm and performs the phase recovery and amplitude compensation simultaneously. The proposed scheme can considerably reduce the logic resources in hardware implementation, has been verified by C++ and Model Sim simulations.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.13 no.11
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• pp.860-867
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• 2003

This paper presents a systematic method measuring a velocity disturbance to design the robust seek loop system of optical disk drives. The velocity disturbance caused by the rotation of a disk has a greater influence on the performance of the seek control loop as the rotational speed increases. Thus, it needs to measure the extent of the velocity disturbance and design the seek control loop based on the measured data. The measurement method of the velocity disturbance is a real-time . method using a measurable velocity and a velocity controller output and is a robust method considering actuator uncertainties. The loop gain adjustment algorithm is introduced to compensate for the actuator uncertainties. The proposed method is implemented by an experimental digital system and is evaluated through an experiment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.13-21
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• 2011

In this paper, the CMOS programmable interface circuit for MEMS gyroscope is presented, and evaluated with the MEMS sensing element. The circuit includes the front-end charge amplifier with 10 bit programmable capacitor arrays, 9 bit DAC for accurate offset calibration, and 10 bit PGA for accurate gain calibration. The self oscillation loop with automatic gain control operates properly. The offset error and gain error after calibration are measured to be 0.36 %FSO and 0.19 %FSO, respectively. The noise equivalent resolution and bias instability are measured to be 0.016 deg/sec and 0.012 deg/sec, respectively. The calibration capability of this circuit can reduce the variations of the output offset and gain, and this can enhance the manufacturability and can improve the yield.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.34-41
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• 2011

This paper presents a wide tuning range, fine-resolution DCO (Digitally Controlled Oscillator) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. To cover the wide tuning range, an automatic three-step coarse tuning scheme is proposed. The DCO total frequency tuning range is 1.4 GHz (2.1 GHz to 3.5 GHz), it is 58 % at 2.4 GHz. An effective frequency resolution is 0.14 kHz/LSB. The proposed DCO is implemented in 0.13 ${\mu}m$ CMOS process. The total power consumption is 6.6 mW from a 1.2 V supply voltage. The phase noise of the DCO output at 2.4 GHz is -120.67 dBc/Hz at 1 MHz offset.

• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.1
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• pp.10-18
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• 2007

In this paper, we extend the multiple time scale control framework to window-based congestion control, in particular, TCP. This is performed by interfacing TCP with a large time scale control module which adjusts the aggressiveness of bandwidth consumption behavior exhibited by TCP as a function of "large time scale" network state. i.e., conformation that exceeds the horizon of the feedback loop as determined by RTT. Performance evaluation of multiple time scale TCP is facilitated by a simulation bench-mark environment which is based on physical modeling of self-similar traffic. If source traffic is not extended exceeding, when RTT is 450ms, in self similar burst environment, performance gain of TCP-SSC is up to 45% for ${\alpha}$=1.05. However, its is acquired only 20% performance gain for ${\alpha}$=1.95 relatively. Therefore we showed that by TCP-MTS at large time scale into a rate-based feedback congestion control, we are able to improve two times performance significantly.