• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.12 no.2
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• pp.30-37
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• 2013

An extended loop antenna, to be continued BLA(Branch Loop Antenna) in the previous volume, for the mobile handset is designed in this paper. It's introduced an ELA(Extended Loop Antenna) that is added extended loops to rectangular loop, and verified antenna performances for applying to mobile handset. Extended loops are located upside, left and right side of rectangular loop, and low resonance is obtained by the length of line. Multiple resonances are established by the extended loops, and obtained the desired service bands by the connection points and lengths. By the implementation and measurement for the multiband ELA, it's showed -3.0~-1.46dBi average gains with 50.15~71.41% efficiencies at CDMA/GSM frequency band, and -8.28~-1.7dBi average gains with 14.87~67.68% efficiencies at DCS/USPCS/WCDMA frequency band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.65-70
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• 2008

A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1935-1940
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• 2016

This paper proposes a phase-locked loop (PLL) to minimize the loop filter output voltage fluctuation by using a comparator including RC time constant circuits. The voltage variation of loop filter is inputted to RC time constant circuits which have two RC time constants, large and small. While a small RC time constant circuit quickly conveys the output voltage variation of loop filter, a large RC time constant circuit conveys slowly the output voltage variation of loop filter and its output looks like constant voltage. The output signal of the comparator controls the sub charge pump and reduces the input voltage variation of voltage-controlled oscillator (VCO). Therefore, the proposed PLL generates a phase noise reduced signal. It has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.154-156
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• 2016

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. Sampling and a small size capacitor functioned negative feedback with switch does make it possible to integrate the PLL into a single chip. The proposed PLL is designed by 1.8V 0.18um CMOS process.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11b
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• pp.1387-1390
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• 2002

자바가상머신은 플랫폼에 독립적인 실행을 위해서 바이트코드라고 하는 스택(stack) 기반의 가상 기계어를 사용하므로 실행 속도가 느리다는 단점이 있다. 특히 루프문을 포함하는 자바프로그램을 자바가상머신에서 수행 시키면 루프에 관련된 몇 개의 동일한 바이트코드가 루프의 실행 횟수만큼 반복적으로 인터프리트해서 수행하므로 상당한 성능 저하를 유발한다. 본 논문에서는 이런 비효율적인 성능상의 문제점을 개선하기 위해 루프를 수행하는 새로운 바이트코드를 정의 및 구현하고, 이를 실제 클래스 파일에 적용하기 위한 코드 변경 절차와 방법을 제시한다. 제안된 바이트코드를 사용해서 루프의 처리 속도를 개선할 경우, 클래스 파일의 크기를 줄일 수 있을 뿐만 아니라 간단한 성능 평가를 통해서 자바가상머신의 성능 개선 효과를 확인할 수 있다.

• Broadcasting and Media Magazine
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• v.24 no.4
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• pp.87-101
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• 2019

JVET(Joint Video Experts Team)에서 새로운 비디오 압축 표준으로 진행 중인 VVC(Versatile Video Coding)에서는 HEVC(High Efficiency Video Coding)의 기술을 근간으로 부호화 효율을 높일 수 있는 다양한 새로운 기술들을 채택하고 있다. 인루프 필터(In-Loop Filter)는 복원영상의 화질을 향상시키기 위한 기술로 주관적 화질 개선뿐만 아니라 부호화 효율을 향상시키는 기술로 기존 HEVC의 확장 기술 및 새로운 인루프 필터 기술을 채택하고 있다. 본 고에서는 VVC의 CD에 채택되어 있는 인루프 필터 기술들을 소개한다. 인루프 필터 기술은 HEVC에 채택되어 있는 디블록킹 필터(Deblocking Filter: DF)와 SAO(Sample Adaptive Offset), 새로이 추가된 ALF(Adaptive Loop Filter)의 3가지의 필터와 LMCS(Luma Mapping with Chroma Scaling) 기술을 포함하고 있다. 이들 인루프 필터 기술은 주관적 화질 개선과 부호화 효율을 크게 개선하고 있으며, 2020년 7월 FDIS(Final Draft International Standard) 완료를 앞두고 인루프 필터링의 다양화로 인한 성능과 복잡도를 고려한 간소화 및 병렬처리 등의 고속화에 대한 표준화가 지속적으로 이루어질 전망이다.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.04a
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• pp.239-242
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• 2001

일반적인 응용 프로그램에서 병렬성이 많은 구조는 루프 구조이며, 루프를 병렬로 처리하기 위해 동기화가 필요하다. 본 논문에서는 다중첨자를 갖는 1차원 배열의 루프의 병렬화를 위해 다수 개의 동일한 종속값을 이용하여 종속함수를 생성하고 이를 이용하여 종속관계가 성립하지 않는 비종속 구간(Non-dependence part)을 구한다. 그리고 동일한 값을 가지는 복수개의 종속값 간의 동기화는 외부루프 분할 기법을 이용하여 간소화 한 후 단일 첨자를 갖는 루프에 동기화를 수행하는 기법을 제시한다.

• 한국ITS학회:학술대회논문집
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• 2004.11a
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• pp.186-191
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• 2004

• Journal of KIISE:Software and Applications
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• v.29 no.11
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• pp.826-836
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• 2002

We need an enormous amount of memories for name spaces as well as additional processors if we are to effectively exploit a massively parallelism in nested loops of functional languages such as Id. If there is no sufficient amount of memories enough to exploit that parallelism, the execution of programs can be aborted during the unfolding of loops. Additionally, if loops are overunfolded, compared with the number of processors available, the system performance can be degraded severely due to the overhead of loop unfolding. This paper suggests and analyzes an algorithm which can be used to effectively unfold nested loops of functional languages on multithreaded architectures. This algorithm has a feature to unfold a given nested loop safely and near optimally, considering the system resources of processors and memories available when the loop is to be unfolded.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.71-77
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• 2009

A novel phase-locked loop(PLL) architecture with multiple charge pumps for fast locking has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. The fast locking PLL that changes its loop bandwidth through controlling charge pumps depending on locking status has been designed. The capacitor usually occupying the larger portion of the chip is also minimized with the proposed scheme. Therefore, the PLL size of $990{\mu}m\;{\times}\;670{\mu}m$ including resistors and capacitors at the bandwidth of 29.9KHz has been achieved. It has been fabricated with 3.3V $0.35{\mu}m$ CMOS process. The locking time is less than $6{\mu}s$ with the measured phase noise of -90.45dBc/Hz @1MHz at 851.2MHz output frequency.