• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.11
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• pp.2009-2014
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• 2017

A novel structure of phase locked loop (PLL) with a time constant comparator and a current compensator has been proposed. The proposed PLL uses small capacitors which are impossible for stable operation in a conventional PLL. It is small enough to be integrated into a single chip. The time constant comparator detects the loop filter output voltage variations using signals which are passed through small and large RC time constants. The signal from the large RC time constant node is the average of the loop filter output voltage. The output voltage of another node is approximately equal to the present loop filter voltage. The output of the time constant comparator controls a current compensator and charge/discharge small size loop filter capacitors. It makes the proposed PLL operate stably. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1068-1075
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• 2018

In this paper, a novel PLL has been proposed that reduces the size of the loop filter while suppressing spur by using a VCO with two inputs. Through the stability analysis according to the operating status, the PLL is designed to operate stably after the phase fixing. The capacitor of loop filter usually occupies larger area of PLL. It is a VCO that can reduce the size of the loop filter by increasing the effective capacitance of the capacitor through the simultaneous charge and discharge operation by two charge pumps and has two signals operating in opposite phases. The settling time of set to $80{\mu}s$ approximately by using a LSI(Locking Status Indicator) indicating the phase locking status. The proposed PLL is designed using a supply voltage of 1.8V and a $0.18{\mu}m$ CMOS process.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.4
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• pp.167-172
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• 2023

A low-noise phase-locked loop(PLL) with three negative feedback loops has been proposed. It is not easy to improve noise characteristics with a conventional PLL. The added negative feedback loops reduce the input voltage magnitude of voltage controlled oscillator which determines the jitter characteristics, enabling the improvement of noise characteristics. Simulation results show that the jitter characteristics are improved as a negative feedback loop is added. In the case of power consumption, it slightly rises by about 10%, but jitter characteristics are improved by about two times. The proposed PLL was simulated with Hspice using a 1.8V 180nm CMOS process.

• Journal of Advanced Navigation Technology
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• v.21 no.1
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• pp.43-49
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• 2017

Generally, loop filter based scalar tracking loops (LF-STL) have been used for global positioning system (GPS) signal tracking algorithm. This paper introduces the accuracy and robustness of linear-quadratic-Gaussian based vector tracking loop (LQG-VTL) algorithm instead of LF-STL. To verify the accuracy of LQG-VTL, we confirm that the measurements estimation errors of the LQG based scalar tracking loops (LQG-STL) are improved by more than 60 % compared to LF-STL. Also, when LQG-VTL is used, measurements estimation errors decrease compared to LQG-STL, and position/velocity estimation errors also decrease as the number of satellites increases. To verify the robustness of LQG-VTL, we confirm that LQG-VTL can estimate position/velocity and measurements successively compared to LF-STL in temporal signal attenuation of 30 dB-Hz during 4 seconds.

• Journal of Korean Society of Transportation
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• v.22 no.6
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• pp.121-131
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• 2004

The K-shortest path algorithms are largely classified into two groups: oneis for finding loopless path (simple path), another loop paths. In terms of cimputational complexities, in general the loop-paths-finding ones are considered more efficient and easier to be handled than the loopless-paths-finding. The entire path deletion methods have been known as the best efficient algorithms among the proposed K-shortest path algorithms. These algorithms exploit the K-th network transformation to prevent the same path, which was already selected as the (K-1)th path, from being redetected. Nevertheless, these algorithms have a critical limitationto be applied in the practical traffic networks because the loops, in which the same modes and links can be unlimitedly repeated, are not preventable. This research develops a way to be able to selectively control loop-paths by applying link-label. This research takes an advantage of the link-based shortest path algorithms that since the algorithms can take care of two links simultaneouslyin the searching process, the generation of loops can be controlled in the concatenation process of the searched link and the preceded link. In concatenation of two links, since the precede link can be treated a sub-shortest to this link from the origination, whether both the node and the link of the searched link were already existed or not can be evaluated. Terefore, both the node-loopless path, in which the same node is not appeared, and the link-loopless, in which the same link is not appeared, can be separately controlled. Especially, the concept of the link-loopless path is expended to take into consideration reasonable route choice behaviors such as U-Turn, P-Turn, and Turn-Penalty, which are frequently witnessed in urban traffic network with intersections. The applicability of the proposed method is verified through case studies.

• Journal of Korea Multimedia Society
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• v.12 no.7
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• pp.971-978
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• 2009

The paper is a phase controlled loop antenna for multi-media devices. We developed a phase control loop pattern arrangement methods for loop antenna in mobile devices like as a cell phone and PCS, WCDMA. In the loop antenna pattern, arrange close adhesive the loop antenna pattern $180^\circ$ cycle in wave length, the radiated electro-magnetic wave from close adhesive loop pattern become to coherent wave than the phase controlled loop antenna has high efficiency and high radiation gain. To acquire a wide band width on phase controlled loop antenna, we arrange a multiple phase controlled loop pattern that has a different length each other. Different length for each other loop pattern cause a different frequency that we can acquire a wide band width for loop antenna from close adhesive phase control. In experiment, we designed a CDMA850 mobile multi-media antenna in 20mm$\times$20mm area thickness 0.4mm, the radiation efficiency is over 60% and radiation gain is over 0dBi.

• Journal of the Korea Society of Computer and Information
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• v.13 no.5
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• pp.27-35
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• 2008

The CTOC framework was implemented to efficiently perform analysis and optimization of the Java bytecode that is often being used lately. In order to analyze and optimize the bytecode from the CTOC, the eCFG was first generated. Due to the bytecode characteristics of difficult analysis, the existing bytecode was expanded to be suitable for control flow analysis. and the control flow graph was drawn. We called eCFG(extended Control Flow Graph). Furthermore, the eCFG was converted into the SSA Form for a static analysis. Many loops were found in the conversion program. The previous CTOC performed conversion directly into the SSA Form without processing the loops. However, processing the loops prior to the SSA Form conversion allows more efficient generation of the SSA Form. This paper examines the process of finding the loops prior to converting the eCFG into the SSA Form In order to efficiently process the loops, and exhibits the procedures for generating the loop tree.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.468-469
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• 2008

항공기, 차량, 고속의 비행체 등과 같은 동적인 플랫폼에서 표적을 추적하기 위한 영상 추적 시스템은 시선을 안정화하는 외부의 추적루프와 내부의 안정화 루프를 포함하는 구조로 되어 있다. 2축 김발을 사용하는 영상 추적 시스템의 추적루프는 크게 영상 추적기, 추적 제어기, 안정화 루프 등으로 구성되어 있다. 본 논문에서는 영상 추적 시스템의 추적 제어기를 설계하여 성능을 분석하고, 또한 설계된 제어기를 적용하여 영상 추적기의 시간지연에 의한 추적 루프 특성을 분석하였다. 마지막으로 설계된 추적 제어기를 영상 추적 시스템 시뮬레이터에 적용하여 고기동 고속의 비행체 환경에서 추적 루프 성능을 분석하였다.

• Proceedings of the Korea Multimedia Society Conference
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• 2001.06a
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• pp.16-19
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• 2001

일반적인 응용 프로그램에서 루프는 대부분의 수행시간을 차지하기 때문에 병렬성 추출의 핵심 부분이라 할 수 있다. 병렬성이 많은 구조는 루프 구조이며, 루프를 병렬로 처리하기 위해 각 반복간에 존재하는 데이터의 종속은 프로세서간의 동기화가 필요하다. 본 논문에서는 다중첨자를 갖는 1차원 배열의 루프의 병렬화를 위해 다수 개의 동일한 종속값을 이용하여 종속함수를 생성하고 이를 이용하여 종속관계가 성립하지 않는 비종속 구간(Non-dependence part)을 구한다. 그리고 동일한 값을 가지는 복수개의 종속값 간의 동기화는 외부루프 분할 기법을 이용하여 적은 횟수의 청자가 외부에 위치하도록 하여 간소화한 후 단일 첨자를 갖는 루프에 동기화를 수행하는 기법을 제시한다.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.564-566
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• 1999

계측 시스템이나 시스템 식별을 수행할 때 정확히 모델링 되는 플랜트를 가정할 경우, 입출력 신호간 혹은 상태 변수들 사이의 비선형 함수 관계를 유도해 낼 수 있다. 그런데 특히 비선형 함수가 매우 복잡하여 해를 닫힌 형태로 구할 수 없을 경우 고려하는 변수들 양자간의 수학적 모델링을 기반으로 루프내 변수가 방정식의 해로 수렴하는 대수 루프를 구성할 수 있다. 이는 모델을 정확히 아는 시스템에 대하여 출력으로부터 입력을 추정하는 역시스템(inverse system)을 구성하는 것과 유사하다. 이러한 개념을 응용한 간단한 예로 용량형 센서의 입출력 비선형성을 제거해주는 역시스템을 대수 루프를 통하여 구현하였다. 또한 구현한 루프가 항상 유일한 해로 수렴할 수 있도록 하는 조건을 구하였다. 해석된 결과를 바탕으로 구현된 루프가 컴퓨터 시뮬레이션 및 아날로그 회로 실험에서도 잘 동작함을 검증하였다. 시뮬레이션 결과로 보인 잡음에 대한 강인성과 실제 회로 실험 결과는 대수 루프의 구현이 실제 용량형 센서 등에 용이하게 적용될 수 있음을 보여준다.