• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1C
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• pp.40-44
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• 2010

The timing error detector(TED) employed in the closed loop type timing synchronization scheme for an MQASK all digital receiver suffers from the selfnoise-induced timing jitter. To eliminate the timing jitter a prefilter can be added in front of the TED. The prefilter method, however, degrades the stability and timing acquisition performance due to the loop delay and increases the complexity of the synchronizer. This paper proposes a polyphase filter type resampler approach to optimize the performance and architecture of the synchronizer simultaneously. The proposed scheme uses two resamplers which performs matched filtering and matched prefiltering so that the loop delay is minimized with minimal hardware resources. Simulation results showed an excellent acquisition performance with reduced timing jitter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.585-593
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• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1421-1432
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• 1994

The optimum design and performance of noncoherent TDL considering the effect of distortions due to the IF bandpasss filters are described. NRZ data and ideal filter is presumed in the simulation. The optimum filter bandwidth is calculated in the sense of minimizing the loop's squaring loss, which is equivalent to minimizing the loop's tracking jitter for a given data rate and data signal-to-noise ratio. As a result, the optimum filter bandwidth depends on the signal-to-noise ratio, and is obtained in the range of about 1-2 times of the data rate.

• Journal of Korean Society of Transportation
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• v.20 no.5
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• pp.163-174
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• 2002

Speeding has been reported as one of the major causes for fatal traffic accidents in Korea. The resolution against this dangerous speeding comes to make the automated speed enforcement system an enforcement tool. The speed detection device, which measures speeds of each incoming vehicles using double loop sensors, requires high accuracy. The object of this study is to develop an accurate speed measurement algorithm using double loop detectors. Some important findings are summarized as follows: 1) It was found that speed measurement errors are caused by scanning rate, distance of two loops, irregular vehicle trajectories, multiple vehicles in detection zone. 2) A proposed algorithm using two signal set proved to reduce variance as well as mean of speed measurement. 3) A proposed filtering algorithm was effective to filter irregular driving vehicles and multiple vehicles in detection zone. A comprehensive field test of developed algorithm resulted in significant improvement of speed measurement accuracy.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.543-545
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• 2017

This paper describes the SAO hardware architecture design for high performance in-loop filters. SAO is an inner module of in-loop filter, which compensates for information loss caused by block-based image compression and quantization. However, HEVC's SAO requires a high computation time because it performs pixel-unit operations. Therefore, the SAO hardware architecture proposed in this paper is based on a $4{\times}4$ block operation and a 2-stage pipeline structure for high-speed operation. The information generation and offset computation structure for SAO computation is designed in a parallel structure to minimize computation time. The proposed hardware architecture was designed with Verilog HDL and synthesized with TSMC chip process 130nm and 65nm cell library. The proposed hardware design achieved a maximum frequency of 476MHz yielding 163k gates and 312.5MHz yielding 193.6k gates on the 130nm and 65nm processes respectively.

• Journal of Broadcast Engineering
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• v.15 no.5
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• pp.697-702
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• 2010

Contour artifact is known as the unintentional result of quantizing a flat area that has smooth gradients. In this letter, a decontouring algorithm is proposed to efficiently remove false contours that occur in typical block-based video coding applications. First, the algorithm goes through a refinement stage to determine candidate blocks probably having noticeable false contours with different kinds of features in a block. Then, pseudo-random noise masking is applied to those blocks to mitigate the contour artifacts. This block-based selective decontouring can efficiently remove the unnecessary processing of those blocks that have no false contour, which incidentally ensures a minor penalty in visual quality and computational complexity. The proposed algorithm was demonstrated, integrated into H.264/AVC, that visual quality can be significantly enhanced with an ignorable rate-distortion (RD) loss and an minor increase in computational complexity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• Journal of Broadcast Engineering
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• v.15 no.5
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• pp.617-630
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• 2010

At 37th VCEG meeting in Jan. 2009, Toshiba proposed Quadtree-based Adaptive Loop Filter (QALF). The basic concept of QALF is to apply Wiener filter to decoded image after the conventional deblocking filter and to represent the filter on/off flag data for each basic filtering unit in a more efficient way of quadtree structure. QALF could enhance the compression performance of around more than 9%, but the structure of one filter for a decoded frame leaves room for further improvement in the sense that optimal filter for one region of a frame could quite different from the optimal filter for other parts of a picture. This paper proposes multiple adaptive loop filters for better utilization of local characteristics of decoded frame to optimize the region-based Wiener filters. Additional filters, proposed in this paper, cover separate spatial area of each decoded frame according to the performance of previously designed filter(s) to provide the flexibility of rate-distortion based selection of the number of filters.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.773-782
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• 2018

A frequency-locked loop(FLL) is a negative-feedback system that uses a frequency detector to improve the phase noise of a voltage-controlled oscillator(VCO). In this work, a theoretical analysis of the phase noise of a VCO in an FLL is presented. The analysis shows that the phase noise of the VCO follows the phase noise determined by the frequency detector and the loop filter within the FLL loop bandwidth, while the phase noise of the VCO appears outside the loop bandwidth. Therefore, it is possible to design an FLL that minimizes the phase noise of the VCO based on the theoretical analysis results. The theoretical phase noise results were verified through experiments.