• The Korean Journal of Applied Statistics
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• v.33 no.1
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• pp.47-59
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• 2020

In this paper, we present the longitudinal Markov binary regression model with t-link function when its transition order is known or unknown. It is assumed that logit or probit models are considered in binary regression models. Here, t-link function can be used for more flexibility instead of the probit model since the t distribution approaches to normal distribution as the degree of freedom goes to infinity. A Markov regression model is considered because of the longitudinal data of each individual data set. We propose Bayesian method to determine the transition order of Markov regression model. In particular, we use the deviance information criterion (DIC) (Spiegelhalter et al., 2002) of possible models in order to determine the transition order of the Markov binary regression model if the transition order is known; however, we compute and compare their posterior probabilities if unknown. In order to overcome the complicated Bayesian computation, our proposed model is reconstructed by the ideas of Albert and Chib (1993), Kuo and Mallick (1998), and Erkanli et al. (2001). Our proposed method is applied to the simulated data and real data examined by Sommer et al. (1984). Markov chain Monte Carlo methods to determine the optimal model are used assuming that the transition order of the Markov regression model are known or unknown. Gelman and Rubin's method (1992) is also employed to check the convergence of the Metropolis Hastings algorithm.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.49-58
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• 2016

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.11
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• pp.115-120
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• 2005

This paper describes the design and implementation of engineering model(EM) of Mass Memory Unit(MMU) for Science and Technology Satellite 2(STSAT-2) and the results of integration test. The use of Field-Programmable Gate Array(FPGA) instead of using private electric parts makes a miniaturization and lightweight of MMU possible. 2Gbits Synchronous Dynamic Random Access Memory(SDRAM) module for mass memory is used to store payload and satellite status data. Moreover, file system is applied to manage them easily in the ground station. RS(207,187) code improves the tolerance with respect to Single Event Upset(SEU) induced in SDRAM. The simulator is manufactured to verify receiving performance of payload data.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.5
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• pp.91-103
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• 2015

This paper presents "The 3-User NOR switching channel based on interference decoding with receiver cooperation" in succession to "Jeju Jong Nang channel code I, II". The Jeju Jong Nang code is considered as one of the earliest human binary coded communication (HBCC) in the world with a definite "1" or "0" binary symbolic analysis of switching circuits. In this paper, we introduce a practical example of interference decoding with receiver cooperation based on the three user Jong Nang NOR switching channel. The proposed system models are the three user Jong Nang (TUJN) NOR logic switching on-off, three-user injective deterministic NOR switching channel and Gaussian interference channel (GIC) with receiver cooperation. Therefore, this model is well matched to Shannon binary symmetric and erasure channel capacity. We show the applications of three-user Gaussian interference decoding to obtain deterministic channels which means each receiver cooperation helps to adjacent others in order to increase degree of freedom. Thus, the optimal sum rate of interference mitigation through adjacent receiver cooperation achieves 7 bits.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.3
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• pp.53-61
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• 2006

This paper is proposed adaptive fuzzy-neuro controller for high performance of induction motor drive. The design of this algorithm based on fuzzy-neural network controller that is implemented using fuzzy control and neural network. This controller uses fuzzy nile as training patterns of a neural network. Also, this controller uses the back-propagation method to adjust the weights between the neurons of neural network in order to minimize the error between the command output and actual output. A model reference adaptive scheme is proposed in which the adaptation mechanism is executed by fuzzy logic based on the error and change of error measured between the motor speed and output of a reference model. The control performance of the adaptive fuzzy-neuro controller is evaluated by analysis for various operating conditions. The results of experiment prove that the proposed control system has strong high performance and robustness to parameter variation, and steady-state accuracy and transient response.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.3
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• pp.433-440
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• 2022

High Altitude Long Endurance(HALE) solar powered UAV is the vehicle that flies for a long time as solar power energy sources. It can be used to replace satellites or provide continuous service because it can perform long-term missions at high altitudes. Due to the property of the mission, it is very important for HALE solar powered UAV to have maximum flight time. It is required for mission performance to fly at high altitudes continuously except a return for temporary maintenance. Therefore mission availability time analysis is a critical factor in the commercialization of HALE solar powered UAV. In this paper, we presented an analytic model and logic for available time analysis based on the design parameters of HALE solar powered UAV. This model can be used to analyze the possibility of applying UAV according to the UAV's mission in concept design before the UAV detail design stage.

• Proceedings of the Korea Water Resources Association Conference
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• 2021.06a
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• pp.217-217
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• 2021

우리나라 동해 연안에 영향을 미쳤던 역사지진들과 일본에서 진행된 동해에서의 대규모지진에 관한 조사검토회에서 2014년에 보고된 동해 동연부와 남해 남연부 측에 있는 60개의 지진공백역들에 대한 단층매개변수들이 공개되어있어 수치실험을 통해 지진해일의 재해도를 분석하고 있다. 하지만 이러한 단층매개변수 값들에 대한 불확실성이 존재하기에 이를 대비한 지진해일 대책을 세울 필요가 있다. 단층매개변수의 불확실성을 고려하는 방법 중 한 가지는 해당 변수들을 조정하여 Case 모델들을 다양화하는 것이다. 이 때 매개변수의 변동에 대한 기준이 필요하기에 단층매개변수에 대한 민감도 분석이 진행되어야 한다. 본 연구의 최종목표는 지진해일에 대한 위험성에 대비하기 위해 선정된 연구지역에 대하여 단층매개변수들을 조정한 경우별 모델들을 사용한 수치모형 실험을 실행한 후 도출된 지진해일 처오름높이 및 처내림높이 결과를 분석하여 각 단층매개 변수의 지진해일에 대한 민감도를 결정하는 것이며, 최종적으로 확률론적 지진해일 재해도분석(Probabilistic Tsunami Hazard Analysys : PTHA)을 실시할 때 기준이 되는 로직트리를 작성할 때 명확한 근거를 제시한다. 단층매개변수의 민감도 분석은 일본(Goda et al., 2014), 미국(Sepúlveda and Liu, 2016), 뉴질랜드(D. Burbridge et al., 2015) 등에서 연구가 활발하게 이루어졌으며 현재도 활발한 연구가 진행되고 있다. 민감도 분석 과정은 먼저 역사 지진해일과 우리나라 근해에 영향을 미칠 수 있는 지진해일의 단층매개변수 조사한 후 파향선추적모형(wave ray-tracing)의 결과를 정리하여 대상 지역에 영향을 미치는 단층을 선정하고, 선정한 단층들의 단층매개변수 값을 일정한 기준을 두고 조정하여 실시한 지진해일 수치모형 실험에서 계산한 결과값을 분석하여 민감도를 결정한다.

• The Journal of the Korea Contents Association
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• v.16 no.11
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• pp.421-433
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• 2016

Recently, although the interest in transfer and transactions of intangible assets increases, there is no valuation model to objectively assess market value of knowledge and information contents such as electronic databases and the necessity of researches associated is brought up. Therefore, the present study proposes valuation models so as to utilize as objective reference information in the contents market of intangible assets, by assessing the market value of science and technology information contents including patents, academic papers and reports. First, we look into application methods of calculating cash flows by content types out of key variables which has been applied to the present technology valuation, and in case of patents we propose valuation methods based on concepts which are applied in the present technology valuation. Next, in case of both papers and reports, in order to reflect the characteristics of these contents we newly propose qualitative valuation methods which are adjustable based on both technology innovation and market demands indices while estimating the economic life cycle of the technology, and also present the input cost-based calculation method as the calculation method of cash flows. Throughout the study, we could establish frameworks by technology fields and business models applicable such as copyright licensing, transactions of individual science and technology information contents, and expect that more objective and reasonable assessment of content values is accessible.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.479-488
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• 2001

As the SoC designs complexity constantly increases, the simulation that uses their software models simply takes too much time. To solve this problem, FPGA-based logic emulators have been developed and commonly used in the industry. However, FPGA-based logic emulators are facing with the problems of which not only very low FPGA resource usage rate due to the very limited number of pins in FPGAs, but also the emulation speed getting slow drastically as the complexity of designs increases. In this paper, we proposed a new innovative emulation architecture and its software that has high FPGA resource usage rate and makes the emulation extremely fast. The proposed emulation system has merits to overcome the FPGA pin limitation by pipelined ring which transfers multiple logic signal through a single physical pin, and it also makes possible to use a high speed system clock through the intelligent ring topology. In this topology, not only all signal transfer channels among EPGAs are totally separated from user logic so that a high speed system clock can be used, but also the depth of combinational paths is kept swallow as much as possible. Both of these are contributed to achieve high speed emulation. For pipelined singnals transfer among FPGAs we adopt a few heuristic scheduling having low computation complexity. Experimental result with a 12 bit microcontroller has shown that high speed emulation possible even with these simple heuristic scheduling algorithms.

• Journal of KIISE:Software and Applications
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• v.37 no.4
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• pp.239-251
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• 2010

In modern distributed enterprise applications that have multilayered architecture, business entities are a kind of crosscutting concerns running through service components that implements business logic in each layer. When business entities are modified, service components related to them should also be modified so that they can deal with those business entities with new types, even though their functionality remains the same. Our previous paper proposed what we call the DTT (Data Type-Tolerant) component model to efficiently process the variability of business entities, which are data externalized from service components. While the DTT component model, by removing direct coupling between service components and business entities, exempts the need to rewrite service components when business entities are modified, it incurs the burden of implementing data type converters that mediate between them. To solve this problem, this paper proposes a method to use ontology as the metadata of both SCDTs (Self-Contained Data Types) in service components and business entities, and a method to generate data type converter code using the ontology. This ontology-based DTT component model greatly enhances the reusability of service components and the efficiency in processing data variability by allowing the computer to automatically generate data type converters without error.