• Journal of IKEEE
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• v.22 no.4
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• pp.896-900
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• 2018

Traditionally, Linear Shift Feedback Register (LFSR) has been widely employed to implement Cyclic Redundant Check (CRC) codes for a serial input. Since many applications including network and storage systems demand as high throughput as ever, various efforts have been made to implement CRC hardware to support parallel inputs. Among various parallel schemes, the look-ahead scheme is one of the most widely used schemes due to its short critical path. However, it is very cumbersome to design HDL codes for parallel CRC codes since the look-ahead scheme is inevitable to consider how register and input values move in the next cycles. Thus, this paper proposes a novel CRC hardware generator, which automatically produces HDL codes given a CRC polynomial and parallel factor. The experimental results verify the applicability to use the proposed generator by analyzing the synthesis results from the generated HDL code.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.2
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• pp.331-339
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• 2017

This paper proposes a thread pool management technique of an websocket server that is applicable to embedded systems. WebSocket is a proposed technique for consisting a dynamic web, and is constructed using HTML5 and jQuery. Various studies have been progressing to construct a dynamic web by Apache, Oracle and etc. Previous web service systems require high-capacity, high-performance hardware specifications and are not suitable for embedded systems. The node.js which is consist of HTML5 and jQuery is a typical websocket server which is made by open sources, and is a java script based web application which is composed of a single thread. The node.js has a limitation on the performance for processing a high velocity data on the embedded system. We make up a multi-thread based websoket server which can solve the mentioned problem. The thread pool is managed by a bit register and suitable for embedded systems. To evaluate the performance of the proposed algorithm, we uses JMeter that is a network test tool.

• Journal of IKEEE
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• v.27 no.4
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• pp.683-686
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• 2023

In this paper, we designed a Delayed Dual Core Lock-Step (D-DCLS) processor where two cores operate same instructions with delay and the result is compared to mitigate soft errors and common mode failures in automotive electronic systems. Because D-DCLS does not know which core an error occurred in, each core must be recovered to the point before the error occurred, but complex hardware modifications are required to return all intermediate values on the pipeline stage. In this paper, in order for easy hardware implementation, all register values are saved to a buffer whenever a branch instruction is executed. When an error is detected, the saved register values are automatically restored, and then 'BX LR' instruction is executed to return to the last branch point. The proposed D-DCLS processor was designed using Verilog HDL and was confirmed to continue normal operation after automatically recovering error.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.5
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• pp.495-500
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• 1988

The effectiveness of tri layer resist (TLR) technique is compared with that of single layer resist (SLR) technique in order to make a 0.8um pattern with the linewidth deviation of 10 percents. SLR technique is not appropriate to shape the micro-pattern on oxide and aluminum steps because of the standing wave effect and the light scattering effect in shaping the resist pattern. On the contrary, the uniform line with a width of 0.8um on oxide and aluminum steps can be formed by TLR technique, reducting such effects. The planarization and the light absorption coefficient of the bottom layer resist in TLR are optimized by exposing it to ultra violet light after baking it for 30min at 230\ulcorner. An uniform line with a width of 0.8um on oxide step is defined with the light absorption coefficient of 0.85 whereas that on aluminum step is defined with 0.95.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.1
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• pp.19-22
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• 1978

A modular microcomputer system based on the Intel 8080 microprocessor is designed. Each module communicate via common bus system. The different modules can be placed anywhere on the bus. Address for memory and I/O modules are determined by switch registers situated on the modules. The system is intended to be used as a base equipment for continuing study, expansion, development and for teaching students.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.1
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• pp.12-18
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• 1978

From the state table of sequential machines, Roomers) obtained minimal k co-mapping chain(k-CC) and proposed an algorithm obtaining binary partitions which were seed partitions of S-shift registers. By comparing and processing bits simply, this paper obtained two different algorithms more efficient than that of Roome's for obtaining such binary partitions and defined the concept of the triple pair of the basis partitions. By using the concept, given set of basis partitions was reduced to the set containing elements of the triple pair only and the algorithm became quite simple.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.5A
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• pp.879-888
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• 2001

본 논문에서는 무선 LAN의 MAC 계층 프로토콜을 고속으로 처리하는 MAC 기능 칩을 개발하였다. 개발된 MAC 칩은 CPU와의 인터페이스를 위한 제어 레지스터들과 인터럽트 체계를 가지고 있으며, 프레임 단위로 송수신 데이터를 처리한다. 또한 PFDM 방식 물리계층 모뎀을 위한 직렬전송 인터페이스를 가지고 있다. 개발된 MAC 칩은 크게 프로토콜제어기능 블록, 송신기능 블록 및 수신기능 블록 등으로 구성되었으며, IEEE 802.11 규격에 제시된 대부분의 DCF 기능을 지원한다. 구현된 MAC 칩의 동작을 검증하기 위해 RTS-CTS 절차 기능, IFS(Inter Frame Space) 기능, 액세스 절차, 백오프 절차, 재전송 기능, 분할된(fragmented) 프레임 송수신 기능, 중복수신 프레임 검출 기능, 가상 캐리어 검출기능(NAV 기능), 수신에러 발생 경우 처리 기능, Broadcast 프레임 송수신 기능, Beacon 프레임 송수신 기능, 송수신 FIFO 동작 기능 등을 시뮬레이션을 통해 시험하였으며, 시험 결과 모두 정상적으로 동작함을 확인하였다. 본 논문을 통해 개발된 MAC 기능 칩을 이용할 경우 고속 무선 LAN 시스템의 CPU 부하(load)와 펌웨어의 크기를 크게 줄일 수 있을 것으로 기대된다.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2005.11a
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• pp.339-342
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• 2005

동적 부분 재구성은 FPGA 칩에 구현된 디자인에서 변경이 필요한 부분만 재구성하여 줌으로써 실시간적 재구성을 가능하게하는 방법이다. 동적 부분 재구성에 대한 많은 연구를 통하여 게이트 수준의 부분 재구성이 가능하지만, 설계 복잡도가 큰 시스템을 설계시에 게이트 수준의 부분 재구성 방법은 부적적하다. 본 논문에서는 Xilinx에서 제고하는 버스 매크로를 사용하여 모듈 기반의 부분 재구성 기법에 대하여 기술하며, 곱셈기, 레지스터, 그리고 ripple carry adder로 구성된 회로에서 ripple carry adder를 carry lookahead adder로 재구성한다.

• The KIPS Transactions:PartC
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• v.10C no.2
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• pp.233-240
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• 2003

In this paper, an improved architecture of turbo codec for IMT-2000 is proposed. The encoder consists of an interleaver using an on-the-fly type address generator and a modified shift register instead of an external RAM, and the decoder uses a decreased number of RAM. The proposed architecture is simulated with C/VHDL languages, where BER (bit-error-rate) performances are generally in agreement with previous data by varying interaction numbers, interleaver block sizes and code rates.