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http://dx.doi.org/10.3745/KIPSTC.2003.10C.2.233

Architecture Design of Turbo Codec using on-the-fly interleaving  

Lee, Sung-Gyu (삼성전자)
Song, Na-Gun (홍익대학교 전자전기공학과)
Kay, Yong-Chul (홍익대학교 전자전기공학과)
Publication Information
The KIPS Transactions:PartC / v.10C, no.2, 2003 , pp. 233-240 More about this Journal
Abstract
In this paper, an improved architecture of turbo codec for IMT-2000 is proposed. The encoder consists of an interleaver using an on-the-fly type address generator and a modified shift register instead of an external RAM, and the decoder uses a decreased number of RAM. The proposed architecture is simulated with C/VHDL languages, where BER (bit-error-rate) performances are generally in agreement with previous data by varying interaction numbers, interleaver block sizes and code rates.
Keywords
Turbo Codec; On-the-fly Interleaving; Error Correction;
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