• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.51-52
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• 2005

Phosphorus doped ZnO thin films on (001) $Al_2O_3$ substrate have been prepared by a pulsed laser deposition (PLD) technique using a Nd:YAG laser. After deposition, phosphorus doped ZnO thin films have been annealed in vacuum, air, nitrogen, and oxygen ambients using pulsed Nd:YAG laser. We report the electrical properties of phosphorus doped ZnO thin films with the variation of the laser annealing conditions for the applications of optoelectronic devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.31-36
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• 2004

we developed a technique to manufacture more reliable polycrystalline silicon TFT-LCDs using UV cleaning and buffered oxide etch(BOE) cleaning which remove the native oxide of the silicon surface before laser annealing. To investigate the effects of pre-treatments on the surface roughness of polycrystalline silicon, we measured atomic force microscopy(AFM). Also the electrical characteristics of polysilicon TFTs, breakdown characteristic and switching Performance, were tested for various pre-treatment conditions and several locations in large glass substrate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.1
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• pp.75-78
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• 2002

Si thin films on p-type (100) Si substrate have been prepared by a pulsed laser deposition technique using a Nd:YAG laser. The pressure of the environmental gas during deposition was 1 Torr. After deposition, Si thin film has been annealed again at 400-840$^{\circ}C$ in nitrogen ambient. Strong blue photoluminescence (PL) have been observed at room temperature. We report the PL properties of Si thin films with the variation of the annealing temperature.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.12
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• pp.559-561
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• 2003

We report a new excimer laser annealing method which successfully results in a single grain boundary formation in the channel of polycrystalline silicon thin film transistor. The proposed method is based on lateral grain growth and employs aluminum patterns which act as selective beam mask and lateral heat sink. The maximum grain size obtained by the proposed method is about 1.6${\mu}{\textrm}{m}$ in the length. The grainboundaries should be arranged parallel with the direction of current flow for the best device performance, so we propose a new device fabrication method and a new poly-Si TFT structure. Poly-Si TFT fabricated by the proposed method exhibits considerably improved electrical characteristics, such as high field effect mobility exceeding 240 $cm^2$/Vsec.

• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.54-57
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• 2004

ZnO thin films on (001) sapphire substrates have been deposited by pulsed laser deposition(PLD) technique using an Nd:YAG laser with a wavelength of 266 m. During deposition, the experiment of the deposition of ZnO thin films has been performed for substrate temperatures in the range of $400^{\circ}C$ and flow rate of 350 sccm, films have been annealed at various substrate temperatures after deposition. After post-annealing treatment in the oxygen ambient, the structural properties of ZnO thin films were characterized by diffraction (XRD), SEM and the optical of the ZnO were characterized by photoluminescence (PL).

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.6
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• pp.46-53
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• 1998

A new method to form the double structured active layers of a-Si/a-SiN$_{x}$ of polycrystalline thin film transistor is proposed and poly-Si TFTs employed double structure active film are fabricated. Nitrogen ions were added to bottom amorphous silicon active film(a-SiN$_{x}$ ) and pure a-Si film deposition on a-SiN$_{x}$ was followed. The XeCl excimer laser was irradiated to crystallize double structure active film. The grain growth of upper a-Si film was also promoted in the double structured active layers of a-Si/a-SiN$_{x}$ due to the mitigation of solidification process of lower a-SiN$_{x}$ layer. Our experimental results show that the ratio of NH$_3$/SiH$_4$ is required to maintain below 0.11 for the reduction of contact resistance of n$^{+}$ poly-SiN$_{x}$ layer.r.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1225_1226
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• 2009

유리 기판 상에 이중 게이트 절연막을 가지는 우수한 특성의 P형 엑시머 레이저 어닐링 (ELA) 다결정 실리콘 박막 트랜지스터를 제작하였다. 그리고 P형 짧은 채널 ELA 다결정 실리콘 박막 트랜지스터의 오프 상태 스트레스 하에서의 전기적 특성을 분석하였다. 스트레스하에서 긴 채널에서의 문턱 전압은 양의 방향으로 거의 이동하지 않는 (${\Delta}V_{TH}$ = 0.116V) 반면, 짧은 채널 박막 트랜지스터의 문턱 전압은 양의 방향으로 상당히 이동 (${\Delta}V_{TH}$ = 2.718V)하는 것을 확인할 수 있었다. 이런 짧은 채널 박막 트랜지스터에서 문턱 전압의 양의 이동은 다결정 실리콘 막과 게이트 산화막 사이의 계면에서의 전자 트랩핑 때문이다. 또한, 박막 트랜지스터의 누설 전류는 오프 상태 스트레스 하에서의 채널 영역의 홀 전하로 인하여 온 전류 수준을 감소시키지 않고 억제될 수 있었다. C-V 측정 결과는 계면의 전자 트랩핑이 드레인 접합 영역부근에서 발생한다는 것을 나타낸다.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.25-30
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• 2003

The total relaxed stress in annealing and the thermal strain/stress were obtained from the identification of the residual stress-free state using electronic speckle pattern interferometry (ESPI). The residual stress fields in case of both single and film/substrate systems were modeled using the thermo-elastic theory and the relationship between relaxed stresses and displacements. We mapped the surface residual stress fields on the indented bulk Cu and the 0.5 ${\mu}m$ Au film by ESPI. In indented Cu, the normal and shear residual stress are distributed over -1.7 GPa to 700 MPa and -800 GPa to 600 MPa respectively around the indented point and in deposited Au film on Si wafer, the tensile residual stress is uniformly distributed on the Au film from 500 MPa to 800 MPa. Also we measured the residual stress by the x-ray diffractometer (XRD) for the verification of above residual stress results by ESPI.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.315-318
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• 1999

We have proposed and fabricated the new bottom-gated polycrystalline silicon (poly-Si) thin film transistor (TFT) with a partial amorphous-Si region by employing the selective laser annealing. The channel layer of the proposed TFTs is composed of poly-Si region in the center and a-Si region in the edge. The TEM image shows that the local a-Si region is successfully fabricated by the effective cut out of the incident laser light in the upper a-Si layer. Our experimental results show that the ON/OFF current ratio is increased significantly by more than three orders in the new poly-Si TFT compared with conventional poly-Si TFT. The leakage current is decreased significantly due to the highly resistive a-Si re TFTs while the ON-series resistance of the local a-Si is reduced significantly due to the considerable inducement of electron carriers by the positive gate bias, so that the ON-current is not decreased much.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.1
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• pp.50-54
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• 2018

In this study, a femtosecond laser pre-annealing technology based on indium zinc oxide (IZO) thin-film transistors (TFTs) was investigated. We demonstrated a stable pre-annealing process to analyze the change in the surface structures of thin-films, and we improved the electrical performance. Furthermore, static and dynamic electrical characteristics of IZO TFTs with n-channel inverters were observed. To investigate the static and dynamic responses of our solution-processed IZO TFTs, simple resistor-load-type inverters were fabricated by connecting a $1-M{\Omega}$ resistor. The femtosecond laser pre-annealing process based on IZO TFTs showed good performance: a field-effect mobility of $3.75cm_2/Vs$, an $I_{on}/I_{off}$ ratio of $1.8{\times}10^5$, a threshold voltage of 1.13 V, and a subthreshold swing of 1.21 V/dec. Our IZO-TFT-based N-MOS inverter performed well at operating voltage, and therefore, is a good candidate for advanced logic circuits and display backplane.