• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.66-72
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• 2009

This paper proposes an efficient binary arithmetic encoder for CABAC which is used one of the entropy coding methods for H.264/AVC. The present binary arithmetic encoding algorithm requires huge complexity of operation and data dependency of each step, which is difficult to be operated in fast. Therefore, renormalization exploits 2-stage pipeline architecture for efficient process of operation, which reduces huge complexity of operation and data dependency. Context model updater is implemented by using a simple expression instead of transIdxMPS table and merging transIdxLPS and rangeTabLPS tables, which decreases hardware size. Arithmetic calculator consists of regular mode, bypass mode and termination mode for appearance probability of binary value. It can operate in maximum speed. The proposed binary arithmetic encoder has 7282 gate counts in 0.18um standard cell library. And input symbol per cycle is about 1.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.51-59
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.45-53
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• 2015

Adaptive support-weight based algorithm can produce better disparity map compared to generic area-based algorithms and also can be implemented as a realtime system. In this paper, we propose a realtime system based on geodesic support-weight which performs better segmentation of objects in the window. The data scheduling is analyzed for efficient hardware design and better performance and the parallel architecture for weight update which takes the longest delay is proposed. The exponential function is efficiently designed using a simple step function by careful error analysis. The proposed architecture is designed with verilogHDL and synthesized using Donbu Hitek 0.18um standard cell library. The proposed system shows 2.22% of error rate and can run up to 260Mhz (25fps) operation frequency with 182K gates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.75-82
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• 2008

In this paper, we propose an efficient symbol detection algorithm for multiple-input multiple-output spatial multiplexing (MIMO-SM) systems and present its design and implementation results. By enhancing the performance of the first detected symbol which causes error propagation, the proposed algorithm achieves a considerable performance gain as compared to the conventional sorted QR decomposition (SQRD) based detection and the ordered successive detection (OSD) algorithms. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In case of 16QAM MIMO-SM system with 4 transmit and 4 receive ($4{\times}4$) antennas, at $BER=10^{-3}$ the proposed algorithm obtains the gai improvement of about 2.5-13.5 dB over the conventional algorithms. The proposed detection algorithm was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. The results show that the proposed algorithm can be implemented without increasing the hardware costs significantly.

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.220-226
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• 2010

In this paper, an low power symbol detector is proposed for MIMO communication system with two transmit and two receive antennas. The proposed symbol detector can support both the spatial multiplexing (SM) mode and spatial diversity (SD) mode for MIMO transmission technique, and shows the optimal maximum likelihood (ML) performance. Also, by sharing the hardware block and using the dedicated clock MIMO modes, the power of the proposed architecture is dramatically decreased. The proposed symbol detector was designed in hardware description language (HDL) and synthesized to logic gates using a $0.13-{\mu}m$ CMOS standard cell library. The power consumption was estimated by using Synopsys Power CompilerTM, which is reduced by maximum 85%, compared with the conventional architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1082-1088
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• 2005

Generating fast round key in AES Rijndael algorithm using three key sizes, such as 128, 192, and 256-bit keys is a critical factor to develop high throughput AES processors. In this paper, we propose on-the-fly round key generator which is applicable to the pipelined and non-pipelined AES processor in which cipher and decipher nodes must be implemented on a chip. The proposed round key generator has modular and area-and-time efficient structure implemented with simple connection of two key expander modules, such as key_exp_m and key_exp_s module. The round key generator for non-pipelined AES processor with support of three key lengths and cipher/decipher modes has about 7.8-ns delay time under 0.25um 2.5V CMOS standard cell library and consists of about 17,700 gates.

• Journal of Cadastre & Land InformatiX
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• v.44 no.2
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• pp.103-112
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• 2014

The objective of this study is to suggest the possibility on land cover classification using hyperspectal imagery on area which includes lands and waters. After atmospheric correction as a preprocessing work was conducted on hyperspectral imagery acquired by airborne hyperspectral sensor CASI-1500, the effect of atmospheric correction to a few land cover class in before and after atmospheric correction was compared and analyzed. As the result of accuracy of land cover classification by highspectral imagery using reference data as airphoto and digital topographic map, maximum likelihood method represented overall accuracy as 67.0% and minimum distance method showed overall accuracy as 52.4%. Also product accuracy of land cover classification on road, dry field and green house, but that on river, forest, grassland showed low because the area of those was composed of complex object. Therefore, the study needs to select optimal band to classify specific object and to construct spectral library considering spectral characteristics of specific object.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.112-121
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• 2002

In this paper, we present a design of a hash processor for data security systems. Two standard hash algorithms, Sha-1(American) and HAS-1600(Korean), are implemented on a single hash engine to support real time processing of the algorithms. The hash processor can also be used as a PRNG(Pseudo-random number generator) by utilizing SHA-1 hash iterations, which is being used in the Intel software library. Because both SHA-1 and HAS-160 have the same step operation, we could reduce hardware complexity by sharing the computation unit. Due to precomputation of message variables and two-stage pipelined structure, the critical path of the processor was shortened and overall performance was increased. We estimate performance of the hash processor about 624 Mbps for SHA-1 and HAS-160, and 195 Mbps for pseudo-random number generation, both at 100 MHz clock, based on Samsung 0.5um CMOS standard cell library. To our knowledge, this gives the best performance for processing the hash algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8A
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• pp.820-826
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• 2007

This paper proposes an enhanced degree computationless modified Euclid's(E-DCME) algorithm and its architecture for Reed-Solomon decoders. The proposed E-DCME algorithm has shorter critical path delay that is $T_{mult}+T_{add}+T_{mux}$ compared with the existing modified Euclid's algorithm and the degree computationless modified Euclid's(DCME) algorithm since it uses new initial conditions. The proposed E-DCME architecture employing a systolic array requires only 2t-1 clock cycles to solve the key equation without initial latency. In addition, the E-DCME architecture consisting of 3t basic cells has regularity and scalability since it uses only one processing element. The E-DCME architecture using the $0.18{\mu}m$ Samsung standard cell library consists of 18,000 gates.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.257-260
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm“Rijndael”. To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation the round transformation block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.