• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.31-42
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• 2010

GPM(Generic Product Model) developed by Hitachi in Japan is a common data model to integrate and share life cycle data of nuclear power plants. GPM consists of GPM core model, an abstract model, implementation language for the model and reference library written in the language. GPM core model has a feature that it can construct a semantic network model consisting of relationships among objects. Initial GPM developed and provided GPML as an implementation language to support the feature of the core model, but afterwards the GPML was replaced by GPM-XML based on XML to achieve data interoperability with heterogeneous applications accessing a GPM data model. However, data models written in GPM-XML are insufficient to be used as a semantic network model for lack of studies which support GPM-XML and enable the models to be used as a semantic network model. This paper proposes OWL as the implementation language for GPM core model because OWL can describe ontologies similar to semantic network models and has an abundant supply of technical standards and supporting tools. Also, OWL which can be expressed in terms of RDF/XML based on XML guarantees data interoperability. This paper uses OWL DL, one of three sublanguages of OWL, because it can guarantee complete reasoning and the maximum expressiveness at the same time. The contents of this paper introduce the way how to overcome the difference between GPM and OWL DL, and, base on this way, describe how to convert the reference library written in GPML into ontologies based on OWL DL written in RDF/XML.

• Korean journal of applied entomology
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• v.57 no.1
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• pp.7-13
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• 2018

Currently, there is no available tool that rapidly diagnoses pine wood nematode (PWN)-infected pine trees in the field. In this study, we synthesized and purified PWN Galectin, which might be an antigen specific to PWN, using the Baculovirus expression system. We used PWN Galectin as an antigen for generating 1,464 fusion hybridoma cell lines secreting monoclonal antibodies (Mabs). Among them, we selected 62 fusion hybridoma cell lines showing high reactivity to PWN Galectin. We further selected 12 fusion hybridoma cell lines showing high reactivity to the standard PWN-infected pine tree phosphate buffered saline (PBS) extract. Additionally, two fusion hybridoma cell lines showing no or extremely low reactivity were used as controls. The selected fusion hybridoma cell lines were subjected to limiting dilutions for selecting and establishing Mab-secreting cell lines showing higher reactivity to the standard PWN-infected pine tree extract than to the standard normal pine tree PBS extract. Moreover, the selected fusion hybridoma cell lines were further selected based on their higher reactivity to PWN protein extracts than to three non-pathogenic nematode protein extracts. The Mab-secreting cell lines established in this study could be used to develop rapid diagnostic tools that can be used in the field or in laboratories for detecting PWN-infected pine trees or PWN.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.72-81
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• 2011

In this paper, we proposed and designed a novel floating point converter which supports single and double precisions of IEEE754 standard. The proposed convertor supports conversions between floating point number single/double precision and signed fixed point number(32bits/64bits) as well as conversions between signed integer(32bits/64bits) and floating point number single/double precision and conversions between floating point number single and double precisions. We defined a new internal format to convert various input types into one type so that overflow checking could be conducted easily according to range of output types. The internal format is similar to the extended format of floating point double precision defined in IEEE754 2008 standard. This standard specifies that minimum exponent bit-width of the extended format of floating point double precision is 15bits, but 11bits are enough to implement the proposed converting unit. Also, we optimized rounding stage of the convertor unit so that we could make it possible to operate rounding and represent correct negative numbers using an incrementer instead an adder. We designed single cycle data path and 5 cycles data path. After describing the HDL model for two data paths of the convertor, we synthesized them with TSMC 180nm technology library using Synopsys design compiler. Cell area of synthesis result occupies 12,886 gates(2 input NAND gate), and maximum operating frequency is 411MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.2A
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• pp.177-183
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• 2009

In this paper, we propose an improved anti-collision algorithm. We have designed an anti-collision unit using this algorithm for the 18000-6 Type C Class 1 Generation 2 standard (Gen2). The Gen2 standard uses a Q-algorithm for incremental method on the Dynamic Slot-Aloha algorithm. It has basically enhanced performance over the Slot-Aloha algorithm. Unfortunately, there are several non-clarified parts: initial $Q_{fp}$ value, weighted C, and the ending point of the algorithm. If an incorrect value is selected, it causes degradation in performance. Thus we propose an improved anti-collision algorithm by clearly defining the vague parts of the existing algorithm. Simulation results showed an improved performance of up to 34.8% using an optimized value of C and the initial $Q_{fp}$ value. With the ending condition, performance is 34.7%. The anti-collision unit is designed using the Verilog HDL. The module was synthesized using Synopsys' Design Compiler and the TSMC $0.2{\mu}m$ standard cell library. The synthesized result yielded 3,847 gates, and was guaranteed under the proposed working frequency of 19.2MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.93-96
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decode. is parameterized for the code rates 1/2, 1/3 and constraint lengths 7, 9, thus it has four operation modes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.150-159
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• 2002

This paper presents the convergence time, SER(Symbol Error Rate), MSE(Mean Square Error), hardware complexity and step-size(${\mu}$) about various LMS(Least Mean Square) algorithms in FS-DFE(Fractionally Spaced-Decision Feedback Equalize) for Cable Modem based on MCNS(Multimedia Cable Network System) DOCSIS(Data Over Cable Service Interface Specification) v1.0/v1.1 standards. We designed and simulated using ${SPW}^{TM}$ and synthesized using STD90 library through ${SYNOPSYS}^{TM}$. And also, we adopted the time-multiplexed multiplication and tap shared architecture in order to achieve the low hardware complexity. Simulation results show that DS-LMS algorithms[1][3] is the optimum solution about performace and hardware size. in high order QAM applications. Finally, we achieved area saving about 58% using DS-LMS algorithm compare with conventional equalizer architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.283-289
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• 2005

In this paper, we propose two efficient symbol detection algorithms for space-frequency OFDM (SF-OFDM) transmit diversity scheme. When the number of sub-carriers in SF-OFBM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithms eliminate this interference in a parallel or sequential manlier and achieve a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithms is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithms achieve the gain improvement of about 3 dB. The symbol detectors with the proposed algorithms are designed in a hardware description language and synthesized to gate-level circuits with the $0.18{\mu}m$ 1.8V CMOS standard cell library. With the division-free architecture, the proposed SF-OFDM-PIC and SF-OFDM-SIC symbol detectors can be implemented using 140k and 129k logic gates, respectively.

• Journal of the Korean Data and Information Science Society
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• v.24 no.5
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• pp.975-987
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• 2013

The Hadoop system was developed by the Apache foundation based on GFS and MapReduce technologies of Google. Many modern systems for managing and processing the big data have been developing based on the Hadoop because the Hadoop was designed for scalability and distributed computing. The R software has been considered as a well-suited analytic tool in the Hadoop based systems because the R is flexible to other languages and has many libraries for complex analyses. We introduced Rhipe which is a R package supporting MapReduce programming easily under the Hadoop system, and implemented a MapReduce program using Rhipe for multiple regression especially. In addition, we compared the computing speeds of our program with the other packages (ff and bigmemory) for processing the large data. The simulation results showed that our program was more fast than ff and bigmemory as the size of data increases.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2465-2473
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems including WiMAX and WLAN. A new design of DFU based on sign-magnitude arithmetic instead of two's complement arithmetic is proposed, resulting in 18% reduction of gate count for 96 DFUs array used in mobile WiMAX LDPC decoder. A multi-mode LDPC decoder for mobile WiMAX standard is designed using the proposed DFU. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 50 MHz clock has 268,870 gates and 71,424 bits RAM, and it is verified by FPGA implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.42-49
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• 2007

CABAC(Context-based Adaptive Binary Arithmetic Coding) among various entropy coding schemes which are used to improve compression efficiency in H.264/AVC has a high hardware complexity and the fast calculation is difficult because data dependancy exists in the bit-serial process. In this paper, the proposed architecture efficiently compose the renormalization process of binary arithmetic encoder which is an important part of CABAC used in H.264/AVC. At every clock cycle, the input symbol is encoded regardless of the iteration of the renormalization process for every input symbol. Also, the proposed architecture can deal with the bitsOutstanding up to 127 which is adopted to handle the carry generation problem and encode input symbol without stall. The proposed architecture with three-stage pipeline has been synthesized using the 0.18um Dongbu-Anam standard cell library and can be operated at 290MHz.