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Proposal Of Optimum Equalizer Hardware Architecture for Cable Modem and Analysis of Various LMS Algorithms  

Cho, Yeon-Gon (성균관대학교 전기전자 및 컴퓨터 공학부)
Yu, Hyeong-Seok (성균관대학교 전기전자 및 컴퓨터 공학부)
Kim, Byung-Wook (성균관대학교 전기전자 및 컴퓨터 공학부)
Cho, Jun-Dong (성균관대학교 전기전자 및 컴퓨터 공학부)
Kim, Jea-Woo (삼성전자 SOC기술연구소)
Lee, Jae-Kon (삼성전자 SOC기술연구소)
Park, Hyun-Chul (ICU)
Abstract
This paper presents the convergence time, SER(Symbol Error Rate), MSE(Mean Square Error), hardware complexity and step-size(${\mu}$) about various LMS(Least Mean Square) algorithms in FS-DFE(Fractionally Spaced-Decision Feedback Equalize) for Cable Modem based on MCNS(Multimedia Cable Network System) DOCSIS(Data Over Cable Service Interface Specification) v1.0/v1.1 standards. We designed and simulated using ${SPW}^{TM}$ and synthesized using STD90 library through ${SYNOPSYS}^{TM}$. And also, we adopted the time-multiplexed multiplication and tap shared architecture in order to achieve the low hardware complexity. Simulation results show that DS-LMS algorithms[1][3] is the optimum solution about performace and hardware size. in high order QAM applications. Finally, we achieved area saving about 58% using DS-LMS algorithm compare with conventional equalizer architecture.
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