• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• Journal of Korean Society of Transportation
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• v.24 no.5 s.91
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• pp.19-33
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• 2006

This paper presents the results of an experimental study on the application of NTCIP protocol to Korean traffic signal control system. For this study the communication Protocol of the existing traffic signal control system was adjusted to meet NTCIP standard. Management information base for Korea real-time traffic signal control system, message library of OER, traffic control center management software supporting SNMP/SFMP Protocol, and agent softwares for local controllers were developed during the experimental study. The applicability test of the adjusted system by NTCIP standard was performed. Fifty eight Percent of communication packets were lost at 2.400bps communication speed, which made the operation impossible. The experimentations with communication speeds 4,800bps and 9,600bps did not cause problems. In conclusion, to apply the NTCIP standard to domestic real-time traffic control system, communication environments need to be upgraded to 4,800bps or higher.

• KIPS Transactions on Software and Data Engineering
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• v.10 no.6
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• pp.243-250
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• 2021

With the increased development of 3D VR applications augmented by recent VR/AR/MR technologies and by the advance of 3D devices, interchangeability and portability of 3D data have become essential. 3D files should be processed in a standard data format for common usage between applications. Providing standardized libraries and data structures along with the standard file format means that a more efficient system organization is possible and unnecessary processing due to the usage of different file formats and data structures depending on the applications can be omitted. In order to provide the function of using a common data file and data structure, this research is intended to provide a programming binding tool for generating and storing standardized data so that various services can be developed by accessing the common 3D files. To achieve this, this paper defines a common data structure including classes and functions to access X3D files with a standardized scheme using the Python programming language. It describes the implementation of a Python language binding viewer, which is an X3D VR viewer for rendering standard X3D data files based on the language binding interface. The VR viewer includes Python based 3D scene libraries and a data structure for creation, modification, exchange, and transfer of X3D objects. In addition, the viewer displays X3D objects and processes events using the libraries and data structure.

• Journal of Practical Engineering Education
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• v.14 no.1
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• pp.1-10
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• 2022

Learning C programming language in electronics education is an important basic education course for understanding computer programming and acquiring the ability to use microprocessors in embedded systems. In order to focus on understanding basic grammar and algorithms, it is a common teaching method to write programs based on C standard library functions in the console window and learn theory and practice in parallel. However, if a student wants to start a project activity or go to a deeper stage after acquiring some basic knowledge of the C language, using only the C standard library function in the console window limits what a student can express or control with the C program. For the purpose of making it easier for a student to use graphics or multimedia resources and increase educational value, this paper studies a case of applying Simple DirectMedia Layer (SDL), an open source software, into the C programming language learning process. The SDL-based programming course applied after completing the basic programming curriculum performed in the console window is introduced, and the educational value is evaluated through a survey. As a result, more than 56% of the respondents expressed positive opinions in terms of improved application ability, stimulating interest, and overall usefulness, and less than 4% of them had negative opinions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.2
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• pp.432-443
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• 2017

The primary goal of the MPEG-H 3D Audio standard is to provide immersive audio environments for high-resolution broadcasting services such as UHDTV. This standard incorporates a wide range of technologies such as encoding/decoding technology for multi-channel/object/scene-based signal, rendering technology for providing 3D audio in various playback environments, and post-processing technology. The reference software decoder of this standard is a structure combining several modules and can operate in various modes. Each module is composed of independent executable files and executed sequentially, real time decoding is impossible. In this paper, we make DLL library of the core decoder, format converter, object renderer, and binaural renderer of the standard and integrate them to enable frame-based decoding. In addition, by measuring the computation complexity of each mode of the MPEG-H 3D-Audio decoder, this paper also provides a reference for selecting the appropriate decoding mode for various hardware platforms. As a result of the computational complexity measurement, the low complexity profiles included in Korean broadcasting standard has a computation complexity of 2.8 times to 12.4 times that of the QMF synthesis operation in case of rendering as a channel signals, and it has a computation complexity of 4.1 times to 15.3 times of the QMF synthesis operation in case of rendering as a binaural signals.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.715-722
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• 2010

This paper describes a hardware design of hash function processor which implements Korean Hash Algorithm Standard HAS-160. The HAS-160 processor compresses a message with arbitrary lengths into a hash code with a fixed length of 160-bit. To achieve high-speed operation with small-area, arithmetic operation for step-operation is implemented by using a hybrid structure of 5:3 and 3:2 carry-save adders and carry-select adder. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency. The designed HAS-160 processor is verified by FPGA implementation, and it has 17,600 gates on a layout area of about $1\;mm^2$ using a 0.35-${\mu}m$ CMOS cell library.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.37-48
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• 2004

The SyncML, the standard synchronization protocol, supports the synchronization of various application services between a client and a server such as an address book, a calendar. Even with this standard protocol, SyncML application developers usually spend a long time and efforts implementing service specific logics and databases. This paper designed and implemented the SDE(Service Development Environment) which is an integrated development environment for SyncML server developers to develop an application service rapidly and correctly. The SDE consists of two components i.e., the Sync Library and the SEG(Sync Engine Generator) tool. To prove the applicability of this study we implemented a SyncML server by using the SDE and also carried out the correctness tests and the performance test. We hope this system helps developers implement mobile application services more efficiently.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.40-47
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• 2006

The finite-field multiplication can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-parallel, bit-serial and systolic multipliers, the proposed multiplier has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.35-42
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• 2007

The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Journal of Korean Society of Steel Construction
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• v.23 no.5
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• pp.637-646
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• 2011

This study is related to the development of a design automation system for the construction design phase of steel structures. The system intended for beam splice friction connections using high-strength bolts. The standard design method and standardization principles that are suggested in the design manual for standard connections using high-strength bolts published by the Korean Society of Steel Construction(KSSC) were reviewed. A structural analysis algorithm was formulated from the review. A design automation system that can automatically calculate the structural design of connections and automatically generate the connection model without separate inputs was developed. To verify the validity of the developed system, its results were compared with the date in the table for the connection design in the Design Manual. The development system was also applied to the sample model. Then the structural design results were compared with the properties of the connection models and drawings created from the results.