• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.151-158
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• 2002

In this paper, Phase locked microwave oscillator having the low phase noise and high stability for digital MMDS down converter was designed. we have been analyzed the low phase noise properties by the active device nonlinear equivalent circuits and derived the necessary and sufficient conditions for high stable voltage control oscillator. And it is applied to phase locked loop, we design the phase locked microwave oscillator of frequency synthesizer. Experimental results of designed phase locked oscillator shows -85dBc/Hz @ 10KHz phase noise properties and simulation result is -90Bc/Hz @ 10kHz respectively we shows that proposed low phase noise and stable conditions of phase locked microwave oscillator can be applied to design the high stable digital MMDS frequency synthesizer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.94-99
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• 2010

This paper presents a design procedure of digitally controlled oscillator(DCO) for power optimization. By controlling coarse tuning bits and fine tuning bits of DCO, the proposed design procedure can optimize the power dissipation and does not affect the LSB resolution, frequency range, linearity, portability. For optimization, the relationship between control bits and power dissipation of the DCO was analyzed. The DCO circuits using and unusing proposed design technique have been designed, simulated and proved using 0.13um, 1.2V CMOS library. The DCO circuit with proposed design technique has operation range between 283MHz and 1.1GHz and has 1.7ps LSB resolution and consumes 2.789mW at frequency of 1GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.242-245
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• 2001

본 논문은 디지털 위성용 하향변환기에 적용되는 고안정 전압제어 마이크로파 발진기의 위상잡음 특성을 분석하였다. 전압제어 마이크로파 발진기는 능동소자의 비선형 등가모델과 궤환회로의 영향을 고려하여 유전체 공진 마이크로파 발진기를 위상잡음과 출력 전력에 절충(trade-off)하여 설계하였고, 13.25GHz의 발진주파수에서 출력이득은 12dBm이고, 위상잡음은 옵셋 주파수 100KHz 에서 -107.91dBc를 보였다. 바렉터 다이오드 동작에 의한 튜닝 범위는 2MHz/V로 위상동기 발진기에 응용할 수 있음을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.34-41
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• 2011

This paper presents a wide tuning range, fine-resolution DCO (Digitally Controlled Oscillator) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. To cover the wide tuning range, an automatic three-step coarse tuning scheme is proposed. The DCO total frequency tuning range is 1.4 GHz (2.1 GHz to 3.5 GHz), it is 58 % at 2.4 GHz. An effective frequency resolution is 0.14 kHz/LSB. The proposed DCO is implemented in 0.13 ${\mu}m$ CMOS process. The total power consumption is 6.6 mW from a 1.2 V supply voltage. The phase noise of the DCO output at 2.4 GHz is -120.67 dBc/Hz at 1 MHz offset.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.4
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• pp.1-9
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• 2010

An LED driving and control circuit has been developed. The LED driver has a new PWM circuit for current control of LED columns with dimming, current and thermal control, and communication functions. The PWM circuit is composed of two ring oscillator and one counter which can be constructed using basic digital logic components. In addition, it has the functions of remote control mode such as ON, OFF, emergency and power saving modes by the serial communication. The PWM generator and control circuit have been designed and fabricated 0.35[${\mu}m$] Magnachip/Hynix digital IC fabrication process. The LED driving and control board using the developed chip is fabricated and tested successfully.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.2
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• pp.95-104
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• 2011

In this paper, the metamaterial transmission line (TL) based on the complementary spiral resonators (CSRs) and interdigital structure is presented for reducing the phase noise of the voltage-controlled oscillator (VCO). The metamaterial TL is realized by adopting the array of the CSRs etched on the ground plane and the interdigital transmission line on the signal plane. The interdigital TL on the signal plane has been used to obtain higher Q value than the conventional TL without the interdigital structure. The resonance properties and inherent saturation of Q value of the proposed metamaterial TL have been analyzed by varying the width of the TL on the signal plane, dimensions of the CSRs, current directions between the CSRs, number of the unit cell-pair of the CSRs, and whether or not there is the interdigital structure in this paper. The phase noise and tuning range of the proposed VCO are -127.50~-125.33 dBc/Hz at 100 kHz and 5.744~5.852 GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.5
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• pp.863-871
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• 2003

In this paper, we design a high stable Ku-band phase-locked dielectric resonant microwave oscillator with the gate voltage controls of p-HEMT. By adapting the nonlinear equivalent elements which affects phase noise of microwave oscillator, we optimize the nonlinear elements of p-HEMT to have low phase noise operation. Using the scattering parameters according to bias voltages, we designed the gate voltage control microwave dielectric resonant oscillator and phase-locked loop circuits is applied to have the high stable operations. Designed microwave oscillator as a local oscillator of digital microwave communication shows that output power is 9.17dBm at 10.75GHz and it's phase noise is -88dBc/Hz at 10KHz offset frequency.

• 전자공학회논문지 IE
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• v.46 no.1
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• pp.1-6
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• 2009

This paper presents the digital PLL architecture and design for improving the frequency detection range and locking time for wide-band frequency synthesizer applications. In this research, a wide-range digital logic quadricorrelator is used for wide-band and fast frequency detector and sigma-delta modulator with 2-bit up-down counter is adopted for DCO control. The proposed digital PLL reduces the phase noise from quantization effect and is suitable for implementation of wide-band fast-locking as well as low power features, which is in high demand for mobile multimedia applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.5
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• pp.739-745
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• 1993

In mobile communication instruments, realization of the frequency synthesizer with high stabililty in temperature is very important. In order to realize a high stability frequency synthesizer, the oscillator providing for reference frequency must be stabilized in various temperature. In accordance to this requirement, the TCXO using digital method is rrealized in this thesis. The DTCXO consists of temperature sensing part, control part and the VCXO. The frequency stability of the realized DTCXO is 0.94 ppm on average. This is an improved result when compared with the 2.5 ppm of the TCXO using analog method.

• 전자공학회논문지 IE
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• v.47 no.2
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• pp.1-7
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• 2010

This paper presents a low power digital PLL architecture and design for implementation of the PLL-based frequency synthesizers. In the proposed architecture, a wide band digital logic quadricorrelator is used for preliminary frequency detector and a narrow band digital logic quadricorrelator is used for final DCO control. Also, a circuit technique for reducing leakage current is adopted in order to minimize the standby mode power consumption of the deactivated block. The proposed digital PLL is designed and verified by MyCAD with MOSIS 1.8V $0.35{\mu}m$ CMOS technology, and the simulation results show that the power consumption can be lowered by more than 20%.