• Journal of the Institute of Convergence Signal Processing
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• v.7 no.4
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• pp.184-188
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• 2006

This paper presents DSP based narrow band satellite communication signal power detector for tracking control of mobile satellite antenna system. An analog filter based conventional power detector has poor performance due to frequency drift of carrier. Also, it is very difficult to change an analog filter bandwidth according to changed bandwidth of transmitted signal. To solve these difficulties, we proposed DSP based signal power detector, which is easy to change bandwidth of filter and to match shifted frequency of carrier. The proposed signal power detector consists of a FFT function to measure frequency drift of carrier, a programmable filter bank function to limit of received signal bandwidth and a power calculation function to measure power of filtered signal in 12-bit linear scale. Test results of implemented signal power detector, based on TMS320C5402 DSP, showed that it satisfied required functions and performances and properly operated.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06c
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• pp.61-64
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• 1994

디지털 신호를 처리하기 위해 특별히 제작된 ADSP-2105는 빠른 Fied-point 연산과 Harvard-architecture로 구조화됐기 때문에 빠른 수행연산을 할 수 가 있다. 본 논문은 이 DSP 프로세서를 이용해 음성신호의 실시간 FFT 분석에 관한 방법을 소개한다. 실시간 FFT 분석기로서의 DSP 보드는 크게 음성신호를 받는 입력부분과 FFT를 계산하는 FFT 부분으로 나뉘어지는데, 입력부분은 AD1849로 8KHz로 데이터를 샘플링해 받게 되었고, FFT 부분은 실제로 DSP가 FFT를 수행하는 부분으로 되어있다. 실시간 처리를 구현하기 위해 입력 부분은 두 개의 뱅크로 만들어 한 뱅크에서 음성신호를 받아들이는 동안에 다른 뱅크에서는 FFT를 계산하도록 되어있어서 DSP 보드는 항시 음성신호를 샘플링 할 수 있는 상태를 유지할 수 있다. 그리고 FFT 처리부는 빠른 처리로 음성신호를 샘츨링할 뱅크가 채워지기 전에 실행되게 프로그램되어 있어 실제적으로 모든 음성데이타를 FFT 하게 되어있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1061-1068
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• 2017

A RVDT is a sensor that measures angular displacement and the output signal of RVDT is a DSBSC-AM signal. For this reason, a DSBSC-AM demodulation processor is required to determine the angular displacement from the output signal. In this paper, DADC(Digital Angle to DC) which extracts the angular displacement from the output signal of a RVDT is implemented based-on modified Costas Loop usually used in the demodulation of DSBSC-AM signal by using FPGA. DADC can used with both 4-wire and 5-wire RVDTs and can exactly compensate the phase difference between the input excitation and output signals of a RVDT unlike the conventional analog RVDT signal conditioners which require external components. Since digital signal processing technique that can enhance the linearity is exploited, DADC shows 0.035% linearity error, which is smaller than 0.005% that of a conventional analog signal conditioner. The DADC are tested in an integrated experimental environment which includes a commercial RVDT sensor, ADC and an analog output block.

• The Magazine of the IEIE
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• v.31 no.6
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• pp.75-95
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• 2004

기존의 아날로그 오디오에 비해 향상된 음질과 넓은 대역폭을 갖는 디지털 오디오는 CD나 DVD 등을 비롯하여, 고선명 TV, 디지털 오디오 방송(DAB) 등 가정용 엔터테인먼트 시스템에서부터, 포터블 오디오 재생기, 이동통신 단말기 등 개인 휴대 장치에 이르기까지 그 응용분야가 다양하다.(중략)

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.7
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• pp.628-637
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• 1990

In this paper we present on architecture for a high sppeed CMOS multiplier which can be used for real-time digital signal processing. And a synthesis method for designing highly parallel algorithms in VLSI is presented. A parallel multiplier design based on the modified Booth's algorithms and Ling's algorthm. This paper addresses the design of multiplier capable of accpting data in 2's complement notation and coefficients in 2's complement notation. Multiplier consists of an interative array of sequential cells, and are well suited to VLSI implementation as a results of their modularity and regularity. Booth's decoders can be fully tested using a relatively small number af test vector.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.93-98
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• 2003

With the improvement of digital signal processors, digital pulse compressor(DPC) is widely used in radar systems. The DPC can be implemented by using FIR filter algorithm in time domain or FFT algorithm in frequency domain. This paper designs an expansible DPC using multiple DSPs. With ADSP-21060 of Analog Devices Inc., the computation time as a function of the number of received range cells and FIR filter tap is compared and analyzed in time domain using C-language and assembly language. therefore, when radar system parameters are determined, the number of DSP's required to implement DPC can be easily estimated.

• Journal of Broadcast Engineering
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• v.9 no.4 s.25
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• pp.357-370
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• 2004

In this paper we propose Digital Signal Processing (DSP) techniques for the Equalization Digital On-Channel Repeater(EDOCR) in the ATSC digital TV (DTV) System. DSP techniques consist of demodulation. baseband equalization, and remodulation. Since the time delay caused by signal processing in the EDOCR can seriously affect the performance of ATSC legacy receivers, it is required that the processing time should be minimized as much as possible. To achieve this goal, we focus on the reduction of the EDOCR's time delay with the minimization of its performance degradation. In addition, we present recommended proper parameters for hardware implementation based on extensive simulation result.

• Korean Journal of Optics and Photonics
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• v.13 no.5
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• pp.377-383
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• 2002

An all-digital closed-loop (ADCL) signal processor for an open-loop FOG was developed to replace the analog circuitry of a Digital Phase Tracking (DPT) signal processor with new digital circuitry. When the ADCL signal processor without a stabilizer for fiber phase modulator (FPM) was attached to the FOG, temperature drift of FOG was about 0.26$\mu$rad/$^{\circ}C$, which makes the FOG unusable in medium or higher-grade applications. This drift was due to variations of phase modulation amplitude and phase delay of the FPM. The stabilizer controls its phase modulation amplitude and phase delay by regulating the ratio of harmonics of the FOG output. Thus, the stabilizer reduces the drift of the FOG to negligible.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.183-186
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• 2004

본 논문에서는 수중 초음파 통신용 QPSK 버스트 수신기를 DSP시스템을 이용하여 구현하기위한 시스템 설계에 대하여 논한다. 본 논문에서 고려하는 시스템은 25kHz의 반송주파수를 사용하고, 심벌율은 5kHz이며, 데이터 전송율은 10,000bps이다. 송신기에서 심벌정보를 전송하기 위해 펄스성형필터를 거친 신호를 디지털 믹서기를 이용하여 디지털 영역에서 반송주파수 대역으로 신호를 변조한 후 200kHz로 샘플링하는 D/A변환기를 이용하여 전송 아날로그 신호를 생성한다. 수신기에서는 수신 신호를 디지털로 처리하기 위하여 100kHz로 free running하는 A/D 변환기를 이용하여 수신 데이터를 얻는다. 수신기에서는 32심벌 길이의 프리앰블을 이용하여 프레임 동기를 찾음과 동시에 개략적인 심벌시간 동기와 위상편이를 추정한다. 추정한 위상편이값은 2차 PLL (phase-looked loop)의 초기값으로 사용하여 위상 추적을 수행하는 전송 시스템이다. 또한, 된 논문에서는 실해역 전송 시험 테이터를 통하여 조류의 변화에 의해 발생하는 Doppler 편이를 보상하기 위하여 PLL이 필수적으로 필요함을 보인다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.1
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• pp.116-126
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• 1997

As the digital system with high sampling rates is required to process numerous data, it is difficult to realize the real time processing for this system. By using the nonlinear energy tracking signal operator, in this paper four kinds of AM/FM demodulators are proposed and designed by the undersampling scheme of decreasing the sampling rate. Particularly, the undersampling frequency and 3dB bandwidth are controllable of these systems and their conditions are respectively. Through the analysis of the designed detectors, useful results are obtained in respect to characteristics and errors.