• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2001.06a
• /
• pp.101-104
• /
• 2001

In this paper, we propose the Digital Automatic Gain Controller for IEEE 802.11a High-speed Physical Layer in the 5 GHz Band. The input gain is estimated by calculating the energy of the training symbol that is a synchronizing signal. The renewal gain is calculated by comparing the estimated gain with the ideal gain. The renewal gain is converted into the controlled voltage for GCA to reduce or amplify the input signals. We used a piecewise-linear approximation to reduce the hardware size. The gain control is performed seven times to provide more accurate gain control. The proposed automatic gain controller is designed with VHDL and verified by using the Xilinx FPGA.

• Journal of the Institute of Convergence Signal Processing
• /
• v.2 no.4
• /
• pp.71-76
• /
• 2001

In this paper we propose the Digital Automatic Gain Controller for IEEE 802.11a-High-speed Physical Layer in the 5 GHz Band. The input gain it estimated by calculating the energy of the training symbol that it a synchronizing signal. The renewal gain is calculated by comparing the estimated gain with the ideal gain. The renewal gain is converted into the controlled voltage for GCA to reduce or amplify the input signals. We used a piecewise-linear approximation to reduce the hardware size. The gain control is performed seven times to provide more accurate gain control. The proposed automatic gain controller is designed with VHDL and verified by using the Xilinx FPGA.

• Korean Journal of Optics and Photonics
• /
• v.14 no.6
• /
• pp.588-593
• /
• 2003

A signal processor for interferometeric fiber optic sensors, which measure dynamic quantities of frequency up to 1 KHz with high sensitivity, is developed. It is a high-speed version of the all-digital phase tracking (ADPT) processor that was used to measure static or slowly-varying quantities. The processor was applied to a fiber optic Mach-Zehnder interferometer to evaluate the performance. The measured total harmonic distortion was near to -50 ㏈, which is the theoretical limit or the ADPT signal processing.

• Journal of the Institute of Convergence Signal Processing
• /
• v.8 no.3
• /
• pp.205-210
• /
• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.8A
• /
• pp.1259-1264
• /
• 1999

In this paper, the High-speed, Low-power Analog-Digital Conversion Archecture is porposed using the Pipelined archecture for High-speed conversion rate and the Successive-Approximation archecture for Low-power consumption. This archecture is the Successive-Approximation archecture using Pipelined Comparator array to change reference voltage during Holding Time. The Analog-to-Digital Converter for video processing is designed using 0.8${\mu}{\textrm}{m}$ CMOS tchnology. When an 6-bit 10MS/s Analog-to-Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 37dB at a sampling rate of 10MHz with 100KHz sine input signal. The power consumption is 1.46mW at 10MS/s. When an 8-bit 10MS/s Analog-to Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41dB at a sampling rate of 100MHz with 100KHz sine input signal. The power consumption is 4.14m W at 10MS/s.

• The Magazine of the IEIE
• /
• v.15 no.2
• /
• pp.88-101
• /
• 1988

• Journal of Sensor Science and Technology
• /
• v.8 no.1
• /
• pp.69-79
• /
• 1999

The research and implementation was preformed on high-resolution CCTV camera with CCD exclusive DSP conventional analog signal processor CCTV camera has its limit on auto exposure(AE), auto white balance(AWB), back light compensation(BLC) processing, severe distortion and noise of image, manual control parameter setting, etc. In our study, to resolve the problems in conventional CCTV camera, we made it possible to control AE, AWB, BLC automatically by the use of the DSP, which are used exclusively in the CCD camera produced domestically, and the microcontroller. And we utilized the function of screen display of microcontroller for the user-friendly interface to control CCD camera. And the electronic variable resister(EVR) was used to avoid setting parameters manually in the level of manufacturing process. As the result, It became possible to control parameters of the camera by program. And the cost-down effect was accomplished by improving the reliability of parameter values and reducing the efforts in setting parameters.

• Journal of the Korean Society of Manufacturing Technology Engineers
• /
• v.10 no.2
• /
• pp.23-34
• /
• 2001

• 한국지구물리탐사학회:학술대회논문집
• /
• 2005.05a
• /
• pp.187-194
• /
• 2005

A PC-based 8-channel seismic system has been developed and applied for bedrock mapping in near shore environment. The system is composed of an analog signal processor and an A/D converter installed on the computer, and a streamer with the group interval of 5 meters. The system is accomplished with a data acquisition program which controls the system and a data processing software. With the PC-based shallow marine seismic survey system high-resolution 2-D marine seismic profiles which have high S/N ratios can be obtained after appropriate data processing.

• Journal of the Korean Society of Radiology
• /
• v.15 no.1
• /
• pp.1-7
• /
• 2021

In order to acquire an image in a positron emission tomography, it is necessary to draw the position coordinates of the scintillation pixels of the detector module measured at the same time. To this end, in a detector module using a plurality of scintillation pixels and a small number of photosensors, it is necessary to obtain a flood image and divide a region of each scintillation pixel to obtain a position of a scintillation pixel interacting with a gamma ray. Alternatively, when the number of scintillation pixels and the number of photosensors to be used are the same, the position coordinates for the position of the scintillation pixels can be directly acquired as digital signal coordinates. A method of using a plurality of scintillation pixels and a small number of photosensors requires a process of obtaining digital signal coordinates requires a plurality of photosensors and a signal processing system. This complicates the signal processing process and raises the cost. To solve this problem, in this study, we developed a method of obtaining digital signal coordinates without performing the process of separating the planar image and region using a plurality of flash pixels and a small number of optical sensors. This is a method of obtaining the position coordinate values of the flash pixels interacting with the gamma ray as a digital signal through a look-up table created through the signals acquired from each flash pixel using the maximum likelihood function. Simulation was performed using DETECT2000, and verification was performed on the proposed method. As a result, accurate digital signal coordinates could be obtained from all the flash pixels, and if this is applied to the existing system, it is considered that faster image acquisition is possible by simplifying the signal processing process.