• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2149-2151
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• 2003

본 논문에서는 마이컴(PIC16C74)과 Tabu 탐색법 및 지능기법(퍼지 및 신경회로망)을 이용하여 고정밀 제어 및 강인한 제어 성능을 가지는 초소형 DC 모터용 지능형 제어기를 개발하였다. 이를 위해 마이컴(PIC16C74)를 이용한 지능형 제어 알고리즘을 개발하고, 초소형 DC 모터용 드라이브 회로 설계 및 제작하였다. 개발한 초소형 DC 모터 지능형 제어기는 디지털 자동 용접캐리지에 적용할 예정이며, 다른 응용 분야로써는 자동배수장치, 반도체 분야, 산업용 로봇 분야 및 조립자동화 시스템 분야 등에 사용되는 구동모터에 적용함으로서 정밀도와 외부의 잡음에 대한 영향을 경감시켜 안정성과 효율향상 및 에너지절약이 가능할 것이다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.01a
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• pp.185-186
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• 2018

기존의 재활치료기구는 부피가 크고 고비용으로 재활치료센터 운영시간에 맞춰 통원하며 이용해야 하는 불편함이 있었다. 이러한 불편함을 해소하기 위해 제안하는 디지털 서보모터 재활 보조기구는 사용자의 상태에 맞게 전문가와 상의하여 구동수치와 손 안쪽의 와이어의 길이를 수정 한 후 사용하는 것을 원칙으로 사용자가 손가락 끝(지문)에 부착된 감압센서를 누르는 강도와 힘의 유지 유무에 따라 손가락을 굽히거나 펴는 행위를 훈련 할 수 있도록 한 재활치료기구이다. 본 논문의 구현결과는 향후 프로토타입을 보완하여 출력과 운용 방법을 기존과 달리 한다면 다양한 재활기구에 응용될 수 있을 것으로 사료된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.8
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• pp.1847-1853
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• 2014

The PAPR of the input signal is increased due to OFDMA signal in a mobile communication system. High efficiency of a power amplifier, which accounts for power consumption, is a very important key technology. Digital Pre-Distortion techniques were used to improve the linearity of the power amplifier. The Asymmetric Doherty scheme was used to improve the efficiency of the power amplifier. In this paper, we propose a new structure of Asymmetric Doherty. Drive power amplifier part is separated as main path and peak path, and phase shifter is employed to improve power combine characteristics of the Doherty Amplifier. Also, envelope tracking technology for drive gate bais in drive peak amplifier is used to improve efficiency.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.212-213
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• 2010

본 논문에서는 고압 방전등을 위한 2단 저주파식 구형파 전자식 안정기를 제안한다. 안정기는 저주파수 구형파 전류를 램프에게 공급하기 위해 인버터와 PFC 단으로 이루어져 있다. 저주파수로 구동하기 때문에 음향 공진 현상은 발생하지 않는다. 그러나 저주파수 극성 반전시 스파이크 전류가 발생하게 되는데 램프전류에 더해져서 흐르기 때문에 램프의 정격 전력 특성에 나쁜 영향을 미치게 된다. 이에 대한 대책으로 새로운 제어 방식이 안정기를 제안하였다. 제안된 안정기는 HID 램프를 위해 150W의 프로토타입 안정기로부터 시뮬레이션 및 실험적인 결과들에 의해 검증하게 된다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.9
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• pp.825-833
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• 2016

This paper introduces a direct-conversion CMOS RF transmitter for the IEEE 802.15.4 standard with a low-power high-gain up-conversion mixer designed in $0.18{\mu}m$ process. The designed RF DCT(Direct Conversion Transmitter) is composed of differential DAC(Digital to Analog Converter), passive low-pass filter, quadrature active mixer and drive amplifier. The most important characteristic in designing RF DCT is to satisfy the 2.4 GHz Zigbee standard in low power. The quadrature active mixer inside the proposed RF DCT provides enough high gain as well as sufficient linearity using a gain boosting technique. The measurement results for the proposed transmitter show very low power consumption of 7.8 mA, output power more than 0 dBm and ACPR (Adjacent Channel Power Ratio) of -30 dBc.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.1
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• pp.44-49
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• 2011

This paper proposes a robust digital speed regulator for a surface-mounted permanent magnet synchronous motor(SPMSM). The proposed speed controller uses a simple digital load disturbance resistance scheme which does not require a load torque observer, so it can be easily and simply implemented without degrading the control performance. To validate the effectiveness of the proposed control algorithm, experimental results as well as simulation results are shown under motor parameter variations using a prototype SPMSM driving system. Finally, it was confirmed that the proposed method can precisely regulate the speed of the SPMSM.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.403-411
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• 2020

Since the analog circuit of the beta ray sensor circuit for the true random number generator and the power and ground line used in the comparator circuit are shared with each other, the power generated by the digital switching of the comparator circuit and the voltage drop at the ground line was the cause of the decreasein the output signal voltage drop at the analog circuit including CSA (Charge Sensitive Amplifier). Therefore, in this paper, the output signal voltage of the analog circuit including the CSAcircuit is reduced by separating the power and ground line used in the comparator circuit, which is the source of digital switching noise, from the power and ground line of the analog circuit. In addition, in the voltage-to-voltage converter circuit that converts VREF (=1.195V) voltage to VREF_VCOM and VREF_VTHR voltage, there was a problem that the VREF_VCOM and VREF_VTHR voltages decrease because the driving current flowing through each current mirror varies due to channel length modulation effect at a high voltage VDD of 5.5V when the drain voltage of the PMOS current mirror is different when driving the IREF through the PMOS current mirror. Therefore, in this paper, since the PMOS diode is added to the PMOS current mirror of the voltage-to-voltage converter circuit, the voltages of VREF_VCOM and VREF_VTHR do not go down at a high voltage of 5.5V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.384-390
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• 2008

Chaotic OOK modulation method can be used in LDR(Low Data Rate) UWB systems. In this paper, UWB chaotic-OOK transmitter system is designed and verified using TSMC 0.18 um CMOS process. A transmitter system is composed of Quasi-chaotic signal generator, OOK Modulator, and driving amplifier. The traditional chaotic signal generators using analog feedback method is weak to process variation. In order to solve this problem, a quasi-chaotic signal generator using digital feedback technique is get wide band signal and OOK Modulator using T-type switching structure is used to enhance the isolation characteristic. A driving amplifier has differential to single structure to avoid an external balun for low cost communication. The measured output power spectrum of the transmitter meet the FCC regulation and the result of the modulation test at data rate of 20 Kbps, 200 Kbps, 2 Mbps, and 10 Mbps is conformed to LDR UWB system. It is shown that the transmitter in this paper can be used for the UWB chaotic-OOK system.

• Journal of Broadcast Engineering
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• v.22 no.5
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• pp.579-588
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• 2017

Recently, due to the development of network environment, the internet market has been expanding, so it is necessary to standardize the data format and API to exchange information among objects. Therefore, MPEG (Moving Picture Expert Group), an international standardization organization, is establishing the MPEG-IoMT (ISO/IEC 23093) project to standardize the Internet of Things. MPEG-IoMT establishes Core Experiment (CE) and discusses overall data exchange such as data exchange procedure, markup language and communication method. In this paper, core experiments 1, 2, 4, and 5 of the core experiments of MPEG-IoMT will be discussed. The performance information of the sensor, the sensor data, the performance information of the driver, and the exchange procedure of the control command are explained and the exchange of the media additional data is discussed. We compare the markup language and communication method through experiment.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1960_1961
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• 2009

본 논문에서는 PID, PWM, HSC, 컴퓨터와의 호스트 통신, 외부 DAC 인터페이스를 FPGA만을 이용하여 하나의 Chip에 구현하고 DC 서보 모터의 속도를 설정한 제어 상태로 안정화시킬 수 있는 시스템을 구현하고자 한다. 컴퓨터에서 설정한 설정치(SV)와 P, I, D의 이득 값을 호스트 통신으로 데이터 블록은 해당 블록으로 전달하며 DC 서보 모터의 엔코더에서 나오는 $90^{\circ}$ 위상차가 있는 2채널의 펄스는 HSC 블록을 거쳐 프로세스치(PV)를 생성 고 이로부터 얻어진 SV와 PV의 편차(E)를 산출한 후 PID 제어 동작을 수행한다. 그 결과인 조작치(MV)를 PWM 블록에 제공하여 실질적으로 DC 서보 모터를 구동하는 H-bridge 회로를 구동한다. 또한 FPGA 내부의 SV, PV, E, MV를 오실로스코프로 계측하기 위해 DAC 인터페이스 블록을 첨가 하여 외부 디지털 아날로그 변환기(DAC)를 제어 하였다.